ARM64 Instruction Set Reference

This document provides a reference for the AArch64 instruction set architecture.

Table of Contents

• Data Processing
• Branches
• Loads and Stores
• SIMD and Vector
• Floating Point
• System
• Cryptography

Data Processing

Instruction	Description
ADCSBC	Data Processing instruction
ADDSUBG	Data Processing instruction
ADDSUB_EXT	Data Processing instruction
ADDSUB_IMM	Data Processing instruction
ADDSUB_SCALAR	Data Processing instruction
ADDSUB_SHIFT	Data Processing instruction
ADR	Data Processing instruction
ANDOREOR_IMM	Data Processing instruction
ANDOREOR_SHIFT	Data Processing instruction
ARITH1_SCALAR	Data Processing instruction
AUT	Data Processing instruction
CAS	Data Processing instruction
CASP	Data Processing instruction
CCMP_IMM	Data Processing instruction
CCMP_REG	Data Processing instruction
CLREX	Data Processing instruction
CLZ	Data Processing instruction
CMEQ_SCALAR	Data Processing instruction
CMGT_SCALAR	Data Processing instruction
CMZERO_SCALAR	Data Processing instruction
CPY	Data Processing instruction
CRC32	Data Processing instruction
CSEL	Data Processing instruction
DCPS	Data Processing instruction
DIV	Data Processing instruction
DOT_ELEM	Data Processing instruction
DRPS	Data Processing instruction
DSB	Data Processing instruction
DUP_SCALAR	Data Processing instruction
ERET	Data Processing instruction
EXTR	Data Processing instruction
HINT	Data Processing instruction
HLT	Data Processing instruction
INS	Data Processing instruction
INTHORZSCALAR	Data Processing instruction
LS64	Data Processing instruction
LS64V	Data Processing instruction
MINMAX_IMM	Data Processing instruction
MINMAX_REG	Data Processing instruction
MOV	Data Processing instruction
MOV_TOGP	Data Processing instruction
MUL	Data Processing instruction
MULH	Data Processing instruction
MULL	Data Processing instruction
MULL_ELEM	Data Processing instruction
MULLELEMSCALAR	Data Processing instruction
MUL_ELEM	Data Processing instruction
MULELEMSCALAR	Data Processing instruction
PACGA	Data Processing instruction
QADDSUB_SCALAR	Data Processing instruction
QSHLSCALARIMM	Data Processing instruction
RCPC	Data Processing instruction
RCPCU	Data Processing instruction
REV	Data Processing instruction
RMIF	Data Processing instruction
SB	Data Processing instruction
SET	Data Processing instruction
SETF	Data Processing instruction
SHA2_2REG	Data Processing instruction
SHA2_3REG	Data Processing instruction
SHA3_4REG	Data Processing instruction
SHA512_2REG	Data Processing instruction
SHA512_3REG	Data Processing instruction
SHIFTV	Data Processing instruction
SHIFTSCALARIMM	Data Processing instruction
SHLREGSCALAR	Data Processing instruction
SHRNSCALARIMM	Data Processing instruction
SHRSCALARIMM	Data Processing instruction
SM3TT	Data Processing instruction
SM3_3REG	Data Processing instruction
SQDMULH_SCALAR	Data Processing instruction
SQDMULL_SCALAR	Data Processing instruction
SQRDMLAH_SCALAR	Data Processing instruction
SUBP	Data Processing instruction
SVC	Data Processing instruction
SWP	Data Processing instruction
TAGINSERT	Data Processing instruction
TCANCEL	Data Processing instruction
TCOMMIT	Data Processing instruction
TSTART	Data Processing instruction
TTEST	Data Processing instruction
UDF	Data Processing instruction
WFXT	Data Processing instruction
XPAC	Data Processing instruction
XTN_SCALAR	Data Processing instruction
ZIP	Data Processing instruction

ADCSBC

ARM64 ADCSBC instruction

Encoding

Bits	Field	Description
31	sf	1-bit value (0=32-bit, 1=64-bit)
30	op	1-bit value
29	S	1-bit value (0=don't set flags, 1=set flags)
28:21	11010000	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:10	000000	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: B, BL, BX

Variants

Variant	Mnemonic Example	Description
Default	B
Ngc	NGC

Default Operands:

Parameter	Type
Rd	General-purpose register
Rn	General-purpose register
Rm	General-purpose register

Ngc Operands:

Parameter	Type
Rd	General-purpose register
Rn	Zero register
Rm	General-purpose register

---

ADDSUBG

ARM64 ADDSUBG instruction

Encoding

Bits	Field	Description
31	1	Fixed bit pattern
30	op	1-bit value
29:22	01000110	Fixed bit pattern
21:16	uimm6	6-bit value
15:14	op3	Fixed value: 00
13:10	uimm4	4-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: ADD, ADDS

Variants

Variant	Mnemonic Example	Description
Default	ADD

Default Operands:

Parameter	Type
Rd	GP register or SP
Rn	GP register or SP
uimm6	Unsigned immediate
uimm4	Unsigned immediate
op3	Constant value

Required Features

MTE

---

ADDSUB_EXT

ARM64 ADDSUB_EXT instruction

Encoding

Bits	Field	Description
31	sf	1-bit value (0=32-bit, 1=64-bit)
30	op	1-bit value
29	S	1-bit value (0=don't set flags, 1=set flags)
28:21	01011001	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:13	option	3-bit value
12:10	imm3	3-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: ADD, ADDS

Variants

Variant	Mnemonic Example	Description
Default	ADD
Cmp	CMP	Compare variant (sets flags)

Default Operands:

Parameter	Type
Rd
Rn	GP register or SP
Rm	General-purpose register
imm3	Immediate value

Cmp Operands:

Parameter	Type
Rd	Zero register
Rn	GP register or SP
Rm	General-purpose register
imm3	Immediate value

---

ADDSUB_IMM

ARM64 ADDSUB_IMM instruction

Encoding

Bits	Field	Description
31	sf	1-bit value (0=32-bit, 1=64-bit)
30	op	1-bit value
29	S	1-bit value (0=don't set flags, 1=set flags)
28:24	10001	Fixed bit pattern
23:22	shift	Fixed value: 0x
21:10	imm12	12-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: ADD, ADDS

Variants

Variant	Mnemonic Example	Description
Default	ADD
Cmp	CMP	Compare variant (sets flags)
Mov	MOV	Move variant (simplified form)

Default Operands:

Parameter	Type
Rd
Rn	GP register or SP
shift,imm12	Additive immediate

Cmp Operands:

Parameter	Type
Rd	Zero register
Rn	GP register or SP
shift,imm12	Additive immediate

Mov Operands:

Parameter	Type
Rd	GP register or SP
Rn	GP register or SP
shift	Constant value
imm12	Constant value

---

ADDSUB_SCALAR

ARM64 ADDSUB_SCALAR instruction

Encoding

Bits	Field	Description
31:30	01	Fixed bit pattern
29	U	1-bit value (0=signed, 1=unsigned)
28:24	11110	Fixed bit pattern
23:22	size	Fixed value: 11
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:10	100001	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: ADD, ADDS

Variants

Variant	Mnemonic Example	Description
Default	ADD

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

ADDSUB_SHIFT

ARM64 ADDSUB_SHIFT instruction

Encoding

Bits	Field	Description
31	sf	1-bit value (0=32-bit, 1=64-bit)
30	op	1-bit value
29	S	1-bit value (0=don't set flags, 1=set flags)
28:24	01011	Fixed bit pattern
23:22	shift	2-bit value
21	0	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:10	imm6	6-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: ADD, ADDS

Variants

Variant	Mnemonic Example	Description
Default	ADD
Noshift	ADD
Cmp	CMP	Compare variant (sets flags)
Cmp_noshift	CMP
Neg	NEG	Negate variant
Neg_noshift	NEG

Default Operands:

Parameter	Type
Rd	General-purpose register
Rn	General-purpose register
Rm	General-purpose register
imm6	Immediate value

Noshift Operands:

Parameter	Type
Rd	General-purpose register
Rn	General-purpose register
Rm	General-purpose register
imm6	Constant value

Cmp Operands:

Parameter	Type
Rd	Zero register
Rn	General-purpose register
Rm	General-purpose register
imm6	Immediate value

Cmp_noshift Operands:

Parameter	Type
Rd	Zero register
Rn	General-purpose register
Rm	General-purpose register
imm6	Constant value

Neg Operands:

Parameter	Type
Rd	General-purpose register
Rn	Zero register
Rm	General-purpose register
imm6	Immediate value

Neg_noshift Operands:

Parameter	Type
Rd	General-purpose register
Rn	Zero register
Rm	General-purpose register
imm6	Constant value

---

ADR

ARM64 ADR instruction

Encoding

Bits	Field	Description
31	op	1-bit value
30:29	immlo	2-bit value
28:24	10000	Fixed bit pattern
23:5	immhi	19-bit value
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: ADR

Variants

Variant	Mnemonic Example	Description
Default	ADR

Default Operands:

Parameter	Type
Rd	General-purpose register
immlo,immhi

---

ANDOREOR_IMM

ARM64 ANDOREOR_IMM instruction

Encoding

Bits	Field	Description
31	sf	1-bit value (0=32-bit, 1=64-bit)
30:29	opc	2-bit value
28:23	100100	Fixed bit pattern
22	N	1-bit value
21:16	immr	6-bit value
15:10	imms	6-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)
-1	0	Fixed bit pattern
-2	1	Fixed bit pattern
-3	0	Fixed bit pattern
-4	1	Fixed bit pattern
-5	0	Fixed bit pattern
-6	0	Fixed bit pattern
-7	0	Fixed bit pattern
-8	0	Fixed bit pattern
-9	1	Fixed bit pattern
-10	0	Fixed bit pattern
-11	0	Fixed bit pattern
-12	1	Fixed bit pattern

Mnemonic

Examples: AND, ANDS

Variants

Variant	Mnemonic Example	Description
Default	AND
Tst	STR	Test variant (bitwise AND and set flags)

Default Operands:

Parameter	Type
Rd
Rn	General-purpose register
N,immr,imms	Logical immediate

Tst Operands:

Parameter	Type
Rd	Zero register
Rn	General-purpose register
N,immr,imms	Logical immediate

---

ANDOREOR_SHIFT

ARM64 ANDOREOR_SHIFT instruction

Encoding

Bits	Field	Description
31	sf	1-bit value (0=32-bit, 1=64-bit)
30:29	opc	2-bit value
28:24	01010	Fixed bit pattern
23:22	shift	2-bit value
21	N	1-bit value
20:16	Rm	5-bit value (second source register)
15:10	imm6	6-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: AND, ANDS

Variants

Variant	Mnemonic Example	Description
Default	AND
Noshift	AND
Tst	STR	Test variant (bitwise AND and set flags)
Tst_noshift	STR
Mvn	MVN	Move Not variant (inverted move)
Mvn_noshift	MVN
Mov	MOV	Move variant (simplified form)

Default Operands:

Parameter	Type
Rd	General-purpose register
Rn	General-purpose register
Rm	General-purpose register
imm6	Immediate value

Noshift Operands:

Parameter	Type
Rd	General-purpose register
Rn	General-purpose register
Rm	General-purpose register
imm6	Constant value

Tst Operands:

Parameter	Type
Rd	Zero register
Rn	General-purpose register
Rm	General-purpose register
imm6	Immediate value

Tst_noshift Operands:

Parameter	Type
Rd	Zero register
Rn	General-purpose register
Rm	General-purpose register
imm6	Constant value

Mvn Operands:

Parameter	Type
Rd	General-purpose register
Rn	Zero register
Rm	General-purpose register
imm6	Immediate value

Mvn_noshift Operands:

Parameter	Type
Rd	General-purpose register
Rn	Zero register
Rm	General-purpose register
imm6	Constant value

Mov Operands:

Parameter	Type
Rd	General-purpose register
Rn	Zero register
Rm	General-purpose register
imm6	Constant value

---

ARITH1_SCALAR

ARM64 ARITH1_SCALAR instruction

Encoding

Bits	Field	Description
31:30	01	Fixed bit pattern
29	U	1-bit value (0=signed, 1=unsigned)
28:24	11110	Fixed bit pattern
23:22	size	2-bit value (element size)
21:16	100000	Fixed bit pattern
15:14	op	2-bit value
13:10	1110	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: ADD, ADDS

Variants

Variant	Mnemonic Example	Description
Default	ADD

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

---

AUT

ARM64 AUT instruction

Encoding

Bits	Field	Description
31:14	110110101100000100	Fixed bit pattern
13	Z	1-bit value
12	op	1-bit value
11	D	1-bit value
10	M	1-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: B, BL, BX

Variants

Variant	Mnemonic Example	Description
Default	B

Default Operands:

Parameter	Type
Rd	General-purpose register
Rn

Required Features

PAuth

---

CAS

ARM64 CAS instruction

Encoding

Bits	Field	Description
31:30	size	2-bit value (element size)
29:23	0010001	Fixed bit pattern
22	L	1-bit value
21	1	Fixed bit pattern
20:16	Rs	5-bit value
15	o0	1-bit value
14:10	11111	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: B, BL, BX

Variants

Variant	Mnemonic Example	Description
Default	B

Default Operands:

Parameter	Type
Rs	General-purpose register
Rt	General-purpose register
Rn	GP register or SP

Required Features

LSE

---

CASP

ARM64 CASP instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	size	1-bit value (element size)
29:23	0010000	Fixed bit pattern
22	L	1-bit value
21	1	Fixed bit pattern
20:16	Rs	5-bit value
15	o0	1-bit value
14:10	Rt2	Fixed value: 11111
9:5	Rn	5-bit value (first source register)
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: CAS, CASA, CASL, CASAL

Variants

Variant	Mnemonic Example	Description
Default	CAS

Default Operands:

Parameter	Type
Rs	General-purpose register
Rt	General-purpose register
Rn	GP register or SP

Required Features

LSE

---

CCMP_IMM

ARM64 CCMP_IMM instruction

Encoding

Bits	Field	Description
31	sf	1-bit value (0=32-bit, 1=64-bit)
30	op	1-bit value
29:21	111010010	Fixed bit pattern
20:16	imm5	5-bit value
15:12	cond	4-bit value
11:10	10	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4	0	Fixed bit pattern
3:0	nzcv	4-bit value

Mnemonic

Examples: CCM

Variants

Variant	Mnemonic Example	Description
Default	CCMi

Default Operands:

Parameter	Type
Rn	General-purpose register
imm5	Immediate value
nzcv	Immediate value
cond	Condition code

---

CCMP_REG

ARM64 CCMP_REG instruction

Encoding

Bits	Field	Description
31	sf	1-bit value (0=32-bit, 1=64-bit)
30	op	1-bit value
29:21	111010010	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:12	cond	4-bit value
11:10	00	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4	0	Fixed bit pattern
3:0	nzcv	4-bit value

Mnemonic

Examples: CCM

Variants

Variant	Mnemonic Example	Description
Default	CCM

Default Operands:

Parameter	Type
Rn	General-purpose register
Rm	General-purpose register
nzcv	Immediate value
cond	Condition code

---

CLREX

ARM64 CLREX instruction

Encoding

Bits	Field	Description
31:12	11010101000000110011	Fixed bit pattern
11:8	CRm	4-bit value
7:0	01011111	Fixed bit pattern

Mnemonic

Examples: CLREX

Variants

Variant	Mnemonic Example	Description
Default	CLREX

Default Operands:

Parameter	Type
CRm	Constant value

---

CLZ

ARM64 CLZ instruction

Encoding

Bits	Field	Description
31	sf	1-bit value (0=32-bit, 1=64-bit)
30:16	101101011000000	Fixed bit pattern
15:10	opcode	6-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: B, BL, BX

Variants

Variant	Mnemonic Example	Description
Default	B

Default Operands:

Parameter	Type
Rd	General-purpose register
Rn	General-purpose register

Required Features

---

CMEQ_SCALAR

ARM64 CMEQ_SCALAR instruction

Encoding

Bits	Field	Description
31:30	01	Fixed bit pattern
29	U	1-bit value (0=signed, 1=unsigned)
28:24	11110	Fixed bit pattern
23:22	size	Fixed value: 11
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:10	100011	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: STR, STRB, STRH

Variants

Variant	Mnemonic Example	Description
Default	STR

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

CMGT_SCALAR

ARM64 CMGT_SCALAR instruction

Encoding

Bits	Field	Description
31:30	01	Fixed bit pattern
29	U	1-bit value (0=signed, 1=unsigned)
28:24	11110	Fixed bit pattern
23:22	size	Fixed value: 11
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:12	0011	Fixed bit pattern
11	eq	1-bit value
10	1	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: CM

Variants

Variant	Mnemonic Example	Description
Default	CMd

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

CMZERO_SCALAR

ARM64 CMZERO_SCALAR instruction

Encoding

Bits	Field	Description
31:30	01	Fixed bit pattern
29	U	1-bit value (0=signed, 1=unsigned)
28:24	11110	Fixed bit pattern
23:22	size	Fixed value: 11
21:14	10000010	Fixed bit pattern
13:12	op	2-bit value
11:10	10	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: CM

Variants

Variant	Mnemonic Example	Description
Default	CMd

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

---

CPY

ARM64 CPY instruction

Encoding

Bits	Field	Description
31:30	size	Fixed value: 00
29:27	011	Fixed bit pattern
26	o0	1-bit value
25:24	01	Fixed bit pattern
23:22	op1	2-bit value
21	0	Fixed bit pattern
20:16	Rs	5-bit value
15:12	op2	4-bit value
11:10	01	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: CPY

Variants

Variant	Mnemonic Example	Description
Default	CPY

Default Operands:

Parameter	Type
Rd	reggpnozr
Rs	reggpnozr
Rn	reggpnozr

Required Features

MOPS

---

CRC32

ARM64 CRC32 instruction

Encoding

Bits	Field	Description
31	sf	1-bit value (0=32-bit, 1=64-bit)
30:21	0011010110	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:13	010	Fixed bit pattern
12	C	1-bit value
11:10	sz	2-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: B, BL, BX

Variants

Variant	Mnemonic Example	Description
Default	B

Default Operands:

Parameter	Type
Rd	General-purpose register
Rn	General-purpose register
Rm	General-purpose register

Required Features

CRC32

---

CSEL

ARM64 CSEL instruction

Encoding

Bits	Field	Description
31	sf	1-bit value (0=32-bit, 1=64-bit)
30	op	1-bit value
29:21	011010100	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:12	cond	4-bit value
11	0	Fixed bit pattern
10	o2	1-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: Instruction

Variants

Variant	Mnemonic Example	Description
Default	Instruction
Nosel	Instruction
Set	Instruction

Default Operands:

Parameter	Type
Rd	General-purpose register
Rn	General-purpose register
Rm	General-purpose register
cond	Condition code

Nosel Operands:

Parameter	Type
Rd	General-purpose register
Rn	General-purpose register
Rm	@Rn
cond	invcond

Set Operands:

Parameter	Type
Rd	General-purpose register
Rn	Zero register
Rm	Zero register
cond	invcond

---

DCPS

ARM64 DCPS instruction

Encoding

Bits	Field	Description
31:21	11010100101	Fixed bit pattern
20:5	imm16	16-bit value
4:2	000	Fixed bit pattern
1:0	LL	2-bit value

Mnemonic

Examples: DCPS

Variants

Variant	Mnemonic Example	Description
Default	DCPS

Default Operands:

Parameter	Type
imm16	Unsigned immediate

Required Features

---

DIV

ARM64 DIV instruction

Encoding

Bits	Field	Description
31	sf	1-bit value (0=32-bit, 1=64-bit)
30:21	0011010110	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:11	00001	Fixed bit pattern
10	o1	1-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: SDIV, UDIV

Variants

Variant	Mnemonic Example	Description
Default	SDIV

Default Operands:

Parameter	Type
Rd	General-purpose register
Rn	General-purpose register
Rm	General-purpose register

---

DOT_ELEM

ARM64 DOT_ELEM instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01111	Fixed bit pattern
23:22	size	2-bit value (element size)
21	L	1-bit value
20	M	1-bit value
19:16	Rm	4-bit value (second source register)
15:12	opcode	4-bit value
11	H	1-bit value
10	0	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: B, BL, BX

Variants

Variant	Mnemonic Example	Description
Default	B

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
M,Rm	regfplim
H,L,M	velemidx

Required Features

---

DRPS

ARM64 DRPS instruction

Encoding

Bits	Field	Description
31:0	11010110101111110000001111100000	Fixed bit pattern

Mnemonic

Examples: DRPS

Variants

Variant	Mnemonic Example	Description
Default	DRPS

---

DSB

ARM64 DSB instruction

Encoding

Bits	Field	Description
31:12	11010101000000110011	Fixed bit pattern
11:8	CRm	4-bit value
7	1	Fixed bit pattern
6:5	opc	2-bit value
4:0	11111	Fixed bit pattern

Mnemonic

Examples: B, BL, BX

Variants

Variant	Mnemonic Example	Description
Default	B
Ssbb	B

Default Operands:

Parameter	Type
CRm	Unsigned immediate

---

DUP_SCALAR

ARM64 DUP_SCALAR instruction

Encoding

Bits	Field	Description
31:21	01011110000	Fixed bit pattern
20:16	imm5	5-bit value
15:10	000001	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)
-1:-4	0000	Fixed bit pattern

Mnemonic

Examples: DUP

Variants

Variant	Mnemonic Example	Description
Default	DUP

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
imm5	immvidx

---

ERET

ARM64 ERET instruction

Encoding

Bits	Field	Description
31:12	11010110100111110000	Fixed bit pattern
11	A	1-bit value
10	M	1-bit value
9:5	Rn	Fixed value: 11111
4:0	op4	5-bit value

Mnemonic

Examples: B, BL, BX

Variants

Variant	Mnemonic Example	Description
Default	B

Default Operands:

Parameter	Type
{M:0	:1=PAuth}

---

EXTR

ARM64 EXTR instruction

Encoding

Bits	Field	Description
31	sf	1-bit value (0=32-bit, 1=64-bit)
30:23	00100111	Fixed bit pattern
22	N	1-bit value
21	0	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:10	imms	6-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: EXTR

Variants

Variant	Mnemonic Example	Description
Default	EXTR
Ror	RORi

Default Operands:

Parameter	Type
Rd	General-purpose register
Rn	General-purpose register
Rm	General-purpose register
imms	Immediate value

Ror Operands:

Parameter	Type
Rd	General-purpose register
Rn	General-purpose register
Rm	@Rn
imms	Immediate value

---

HINT

ARM64 HINT instruction

Encoding

Bits	Field	Description
31:12	11010101000000110010	Fixed bit pattern
11:5	imm	7-bit value
4:0	11111	Fixed bit pattern

Mnemonic

Examples: HINT # TODO pretty format of immediate

Variants

Variant	Mnemonic Example	Description
Default	HINT
Noops	LDR

Default Operands:

Parameter	Type
imm	Immediate value

Noops Operands:

Parameter	Type
{imm:0	:1=:2=:3=:4=:5=:6=DGH:7=PAuth:8=PAuth:10=PAuth:12=PAuth:14=PAuth:16=RAS:17=SPE:18=TRF:19=GCS:20=:22=CLRBHB:24=PAuth:25=PAuth:26=PAuth:27=PAuth:28=PAuth:29=PAuth:30=PAuth:31=PAuth:32=BTI:34=BTI:36=BTI:38=BTI:40=CHK}

---

HLT

ARM64 HLT instruction

Encoding

Bits	Field	Description
31:21	11010100010	Fixed bit pattern
20:5	imm16	16-bit value
4:0	00000	Fixed bit pattern

Mnemonic

Examples: HLT

Variants

Variant	Mnemonic Example	Description
Default	HLT

Default Operands:

Parameter	Type
imm16	Unsigned immediate

---

INS

ARM64 INS instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	Fixed value: 1
29	op	1-bit value
28:21	01110000	Fixed bit pattern
20:16	imm5	5-bit value
15	0	Fixed bit pattern
14:11	imm4	4-bit value
10	1	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)
-1:-4	0000	Fixed bit pattern

Mnemonic

Examples: INS

Variants

Variant	Mnemonic Example	Description
Elem	INS
Gp	INS

Elem Operands:

Parameter	Type
Rd	Floating-point register
imm5	immvidx
Rn	Floating-point register
imm4	immvidx

Gp Operands:

Parameter	Type
Rd	Floating-point register
imm5	immvidx
Rn	General-purpose register

---

INTHORZSCALAR

ARM64 INTHORZSCALAR instruction

Encoding

Bits	Field	Description
31:30	01	Fixed bit pattern
29	U	Fixed value: 0
28:24	11110	Fixed bit pattern
23:22	size	Fixed value: 11
21:17	11000	Fixed bit pattern
16:12	opcode	Fixed value: 11011
11:10	10	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: ADD, ADDS

Variants

Variant	Mnemonic Example	Description
Default	ADD

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

---

LS64

ARM64 LS64 instruction

Encoding

Bits	Field	Description
31:15	11111000001111111	Fixed bit pattern
14	o1	1-bit value
13:10	0100	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: LDR, LDRB, LDRH

Variants

Variant	Mnemonic Example	Description
Default	LDR

Default Operands:

Parameter	Type
Rt	reggpls64
Rn	GP register or SP

Required Features

LS64

---

LS64V

ARM64 LS64V instruction

Encoding

Bits	Field	Description
31:21	11111000001	Fixed bit pattern
20:16	Rs	5-bit value
15	1	Fixed bit pattern
14:12	op	Fixed value: 01x
11:10	00	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: STR, STRB, STRH

Variants

Variant	Mnemonic Example	Description
Default	STR

Default Operands:

Parameter	Type
Rs	General-purpose register
Rt	reggpls64
Rn	GP register or SP

Required Features

LS64

---

MINMAX_IMM

ARM64 MINMAX_IMM instruction

Encoding

Bits	Field	Description
31	sf	1-bit value (0=32-bit, 1=64-bit)
30	0	Fixed bit pattern
29	S	Fixed value: 0
28:22	1000111	Fixed bit pattern
21:18	opcode	Fixed value: 00xx
17:10	imm8	8-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: Instruction

Variants

Variant	Mnemonic Example	Description
Default	i

Default Operands:

Parameter	Type
Rd	General-purpose register
Rn	General-purpose register
imm8	,bits=8

Required Features

CSSC

---

MINMAX_REG

ARM64 MINMAX_REG instruction

Encoding

Bits	Field	Description
31	sf	1-bit value (0=32-bit, 1=64-bit)
30	0	Fixed bit pattern
29	S	Fixed value: 0
28:21	11010110	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:10	opcode	Fixed value: 0110xx
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: Instruction

Variants

Variant	Mnemonic Example	Description
Default	Instruction

Default Operands:

Parameter	Type
Rd	General-purpose register
Rn	General-purpose register
Rm	General-purpose register

Required Features

CSSC

---

MOV

ARM64 MOV instruction

Encoding

Bits	Field	Description
31	sf	1-bit value (0=32-bit, 1=64-bit)
30:29	opc	2-bit value
28:23	100101	Fixed bit pattern
22:21	hw	2-bit value
20:5	imm16	16-bit value
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: MOV, MOVS, MVN

Variants

Variant	Mnemonic Example	Description
Default	MOV
Dyn	MOV

Default Operands:

Parameter	Type
Rd	General-purpose register
imm16	Unsigned immediate

Dyn Operands:

Parameter	Type
Rd	General-purpose register
imm16	Unsigned immediate
hw	Immediate value

---

MOV_TOGP

ARM64 MOV_TOGP instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29:21	001110000	Fixed bit pattern
20:16	imm5	5-bit value
15:13	001	Fixed bit pattern
12	U	1-bit value (0=signed, 1=unsigned)
11:10	11	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)
-1:-3	000	Fixed bit pattern
-4:-5	00	Fixed bit pattern
-6	1	Fixed bit pattern
-7:-9	000	Fixed bit pattern
-10	0	Fixed bit pattern
-11:-14	1000	Fixed bit pattern
-15	1	Fixed bit pattern

Mnemonic

Examples: MOV, MOVS, MVN

Variants

Variant	Mnemonic Example	Description
Default	MOV

Default Operands:

Parameter	Type
Rd	General-purpose register
Rn	Floating-point register
imm5	immvidx

---

MUL

ARM64 MUL instruction

Encoding

Bits	Field	Description
31	sf	1-bit value (0=32-bit, 1=64-bit)
30:21	0011011000	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15	o0	1-bit value
14:10	Ra	5-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: ADD, ADDS

Variants

Variant	Mnemonic Example	Description
Default	ADD
Mul	M

Default Operands:

Parameter	Type
Rd	General-purpose register
Rn	General-purpose register
Rm	General-purpose register
Ra	General-purpose register

Mul Operands:

Parameter	Type
Rd	General-purpose register
Rn	General-purpose register
Rm	General-purpose register
Ra	Zero register

---

MULH

ARM64 MULH instruction

Encoding

Bits	Field	Description
31	sf	Fixed value: 1
30:24	0011011	Fixed bit pattern
23	U	1-bit value (0=signed, 1=unsigned)
22:21	10	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15	0	Fixed bit pattern
14:10	Ra	5-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: MUL, MULS

Variants

Variant	Mnemonic Example	Description
Default	MUL

Default Operands:

Parameter	Type
Rd	General-purpose register
Rn	General-purpose register
Rm	General-purpose register
Ra	Zero register

---

MULL

ARM64 MULL instruction

Encoding

Bits	Field	Description
31	sf	Fixed value: 1
30:24	0011011	Fixed bit pattern
23	U	1-bit value (0=signed, 1=unsigned)
22:21	01	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15	o0	1-bit value
14:10	Ra	5-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: ADD, ADDS

Variants

Variant	Mnemonic Example	Description
Default	ADD
Mul	ML

Default Operands:

Parameter	Type
Rd	General-purpose register
Rn	General-purpose register
Rm	General-purpose register
Ra	General-purpose register

Mul Operands:

Parameter	Type
Rd	General-purpose register
Rn	General-purpose register
Rm	General-purpose register
Ra	Zero register

---

MULL_ELEM

ARM64 MULL_ELEM instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01111	Fixed bit pattern
23:22	size	2-bit value (element size)
21	L	1-bit value
20	M	1-bit value
19:16	Rm	4-bit value (second source register)
15:12	opcode	4-bit value
11	H	1-bit value
10	0	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: MUL, MULS

Variants

Variant	Mnemonic Example	Description
Default	MUL

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
M,Rm	regfplim
H,L,M	velemidx

---

MULLELEMSCALAR

ARM64 MULLELEMSCALAR instruction

Encoding

Bits	Field	Description
31:30	01	Fixed bit pattern
29	U	Fixed value: 0
28:24	11111	Fixed bit pattern
23:22	size	2-bit value (element size)
21	L	1-bit value
20	M	1-bit value
19:16	Rm	4-bit value (second source register)
15:12	opcode	4-bit value
11	H	1-bit value
10	0	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: MUL, MULS

Variants

Variant	Mnemonic Example	Description
Default	MUL

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
M,Rm	regfplim
H,L,M	velemidx

---

MUL_ELEM

ARM64 MUL_ELEM instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01111	Fixed bit pattern
23:22	size	2-bit value (element size)
21	L	1-bit value
20	M	1-bit value
19:16	Rm	4-bit value (second source register)
15:12	opcode	4-bit value
11	H	1-bit value
10	0	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: MUL, MULS

Variants

Variant	Mnemonic Example	Description
Default	MUL

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
M,Rm	regfplim
H,L,M	velemidx

Required Features

---

MULELEMSCALAR

ARM64 MULELEMSCALAR instruction

Encoding

Bits	Field	Description
31:30	01	Fixed bit pattern
29	U	1-bit value (0=signed, 1=unsigned)
28:24	11111	Fixed bit pattern
23:22	size	2-bit value (element size)
21	L	1-bit value
20	M	1-bit value
19:16	Rm	4-bit value (second source register)
15:12	opcode	4-bit value
11	H	1-bit value
10	0	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: MUL, MULS

Variants

Variant	Mnemonic Example	Description
Default	MUL

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
M,Rm	regfplim
H,L,M	velemidx

Required Features

---

PACGA

ARM64 PACGA instruction

Encoding

Bits	Field	Description
31:21	10011010110	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:10	001100	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: PACIA, PACIB, PACDA, PACDB

Variants

Variant	Mnemonic Example	Description
Default	PACIA

Default Operands:

Parameter	Type
Rd	General-purpose register
Rn	General-purpose register
Rm	GP register or SP

Required Features

PAuth

---

QADDSUB_SCALAR

ARM64 QADDSUB_SCALAR instruction

Encoding

Bits	Field	Description
31:30	01	Fixed bit pattern
29	U	1-bit value (0=signed, 1=unsigned)
28:24	11110	Fixed bit pattern
23:22	size	2-bit value (element size)
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:14	00	Fixed bit pattern
13	op	1-bit value
12:10	011	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: ADD, ADDS

Variants

Variant	Mnemonic Example	Description
Default	ADD

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

QSHLSCALARIMM

ARM64 QSHLSCALARIMM instruction

Encoding

Bits	Field	Description
31:30	01	Fixed bit pattern
29	U	1-bit value (0=signed, 1=unsigned)
28:23	111110	Fixed bit pattern
22:19	immh	4-bit value
18:16	immb	3-bit value
15:13	011	Fixed bit pattern
12	op	1-bit value
11:10	01	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)
-1	0	Fixed bit pattern

Mnemonic

Examples: Instruction

Variants

Variant	Mnemonic Example	Description
Default	i

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
immh,immb	immshiftl

---

RCPC

ARM64 RCPC instruction

Encoding

Bits	Field	Description
31:30	size	2-bit value (element size)
29:21	111000101	Fixed bit pattern
20:16	Rs	Fixed value: 11111
15:10	110000	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: LDR, LDRB, LDRH

Variants

Variant	Mnemonic Example	Description
Default	LDR

Default Operands:

Parameter	Type
Rt	General-purpose register
Rn	GP register or SP

Required Features

LRCPC

---

RCPCU

ARM64 RCPCU instruction

Encoding

Bits	Field	Description
31:30	size	2-bit value (element size)
29:24	011001	Fixed bit pattern
23:22	opc	2-bit value
21	0	Fixed bit pattern
20:12	imm9	9-bit value
11:10	00	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: LDR, LDRB, LDRH

Variants

Variant	Mnemonic Example	Description
Default	LDR

Default Operands:

Parameter	Type
Rt	General-purpose register
Rn	GP register or SP
imm9	Signed immediate

Required Features

LRCPC2

---

REV

ARM64 REV instruction

Encoding

Bits	Field	Description
31	sf	1-bit value (0=32-bit, 1=64-bit)
30:12	1011010110000000000	Fixed bit pattern
11:10	opc	2-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: B, BL, BX

Variants

Variant	Mnemonic Example	Description
Default	B

Default Operands:

Parameter	Type
Rd	General-purpose register
Rn	General-purpose register

---

RMIF

ARM64 RMIF instruction

Encoding

Bits	Field	Description
31	sf	Fixed value: 1
30:21	0111010000	Fixed bit pattern
20:15	imm6	6-bit value
14:10	00001	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4	0	Fixed bit pattern
3:0	mask	4-bit value

Mnemonic

Examples: RMIF

Variants

Variant	Mnemonic Example	Description
Default	RMIF

Default Operands:

Parameter	Type
Rn	General-purpose register
imm6	Immediate value
mask	Immediate value

Required Features

FlagM

---

SB

ARM64 SB instruction

Encoding

Bits	Field	Description
31:12	11010101000000110011	Fixed bit pattern
11:8	CRm	Fixed value: 0000
7	1	Fixed bit pattern
6:5	opc	Fixed value: 11
4:0	11111	Fixed bit pattern

Mnemonic

Examples: B, BL, BX

Variants

Variant	Mnemonic Example	Description
Default	B

---

SET

ARM64 SET instruction

Encoding

Bits	Field	Description
31:30	size	Fixed value: 00
29:27	011	Fixed bit pattern
26	o0	1-bit value
25:24	01	Fixed bit pattern
23:22	op1	Fixed value: 11
21	0	Fixed bit pattern
20:16	Rs	5-bit value
15:12	op2	4-bit value
11:10	01	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: SET

Variants

Variant	Mnemonic Example	Description
Default	SET

Default Operands:

Parameter	Type
Rd	reggpnozr
Rs	reggpnozr
Rn	General-purpose register

Required Features

MOPS

---

SETF

ARM64 SETF instruction

Encoding

Bits	Field	Description
31	sf	Fixed value: 0
30:15	0111010000000000	Fixed bit pattern
14	sz	1-bit value
13:10	0010	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	01101	Fixed bit pattern

Mnemonic

Examples: SETF

Variants

Variant	Mnemonic Example	Description
Default	SETF

Default Operands:

Parameter	Type
Rn	General-purpose register

Required Features

FlagM

---

SHA2_2REG

ARM64 SHA2_2REG instruction

Encoding

Bits	Field	Description
31:24	01011110	Fixed bit pattern
23:22	size	Fixed value: 00
21:14	10100000	Fixed bit pattern
13:12	opcode	2-bit value
11:10	10	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: SHA

Variants

Variant	Mnemonic Example	Description
Default	SHA

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

Required Features

SHA

---

SHA2_3REG

ARM64 SHA2_3REG instruction

Encoding

Bits	Field	Description
31:24	01011110	Fixed bit pattern
23:22	size	Fixed value: 00
21	0	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15	0	Fixed bit pattern
14:12	opcode	3-bit value
11:10	00	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: SHA

Variants

Variant	Mnemonic Example	Description
Default	SHA

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

Required Features

SHA

---

SHA3_4REG

ARM64 SHA3_4REG instruction

Encoding

Bits	Field	Description
31:23	110011100	Fixed bit pattern
22:21	op0	2-bit value
20:16	Rm	5-bit value (second source register)
15	0	Fixed bit pattern
14:10	Ra	5-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: EOR, EORS

Variants

Variant	Mnemonic Example	Description
Default	EOR

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register
Ra	Floating-point register

Required Features

---

SHA512_2REG

ARM64 SHA512_2REG instruction

Encoding

Bits	Field	Description
31:12	11001110110000001000	Fixed bit pattern
11:10	opcode	2-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: Instruction

Variants

Variant	Mnemonic Example	Description
Default	Instruction

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

Required Features

---

SHA512_3REG

ARM64 SHA512_3REG instruction

Encoding

Bits	Field	Description
31:21	11001110011	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15	1	Fixed bit pattern
14	O	Fixed value: 0
13:12	00	Fixed bit pattern
11:10	opcode	2-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: Instruction

Variants

Variant	Mnemonic Example	Description
Default	Instruction

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

Required Features

---

SHIFTV

ARM64 SHIFTV instruction

Encoding

Bits	Field	Description
31	sf	1-bit value (0=32-bit, 1=64-bit)
30:21	0011010110	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:12	0010	Fixed bit pattern
11:10	op2	2-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: V

Variants

Variant	Mnemonic Example	Description
Default	V

Default Operands:

Parameter	Type
Rd	General-purpose register
Rn	General-purpose register
Rm	General-purpose register

---

SHIFTSCALARIMM

ARM64 SHIFTSCALARIMM instruction

Encoding

Bits	Field	Description
31:30	01	Fixed bit pattern
29	U	1-bit value (0=signed, 1=unsigned)
28:23	111110	Fixed bit pattern
22:19	immh	Fixed value: 1xxx
18:16	immb	3-bit value
15:13	010	Fixed bit pattern
12	op	1-bit value
11:10	01	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: Instruction

Variants

Variant	Mnemonic Example	Description
Default	di

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
immh,immb	immshift

---

SHLREGSCALAR

ARM64 SHLREGSCALAR instruction

Encoding

Bits	Field	Description
31:30	01	Fixed bit pattern
29	U	1-bit value (0=signed, 1=unsigned)
28:24	11110	Fixed bit pattern
23:22	size	2-bit value (element size)
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:13	010	Fixed bit pattern
12	R	1-bit value
11	S	1-bit value (0=don't set flags, 1=set flags)
10	1	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: SHL

Variants

Variant	Mnemonic Example	Description
Default	SHL

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

SHRNSCALARIMM

ARM64 SHRNSCALARIMM instruction

Encoding

Bits	Field	Description
31:30	01	Fixed bit pattern
29	U	1-bit value (0=signed, 1=unsigned)
28:23	111110	Fixed bit pattern
22:19	immh	4-bit value
18:16	immb	3-bit value
15:13	100	Fixed bit pattern
12	op	1-bit value
11	R	1-bit value
10	1	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)
-1	0	Fixed bit pattern

Mnemonic

Examples: SHRN

Variants

Variant	Mnemonic Example	Description
Default	SHRNi

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
immh,immb	immshiftr

---

SHRSCALARIMM

ARM64 SHRSCALARIMM instruction

Encoding

Bits	Field	Description
31:30	01	Fixed bit pattern
29	U	1-bit value (0=signed, 1=unsigned)
28:23	111110	Fixed bit pattern
22:19	immh	Fixed value: 1xxx
18:16	immb	3-bit value
15:14	00	Fixed bit pattern
13	o1	1-bit value
12	o0	1-bit value
11:10	01	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: Instruction

Variants

Variant	Mnemonic Example	Description
Default	d

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
immh,immb	immshiftr

---

SM3TT

ARM64 SM3TT instruction

Encoding

Bits	Field	Description
31:21	11001110010	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:14	10	Fixed bit pattern
13:12	imm2	2-bit value
11:10	opcode	2-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: B, BL, BX

Variants

Variant	Mnemonic Example	Description
Default	B

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register
imm2	Immediate value

Required Features

SM3

---

SM3_3REG

ARM64 SM3_3REG instruction

Encoding

Bits	Field	Description
31:21	11001110011	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15	1	Fixed bit pattern
14	O	Fixed value: 1
13:12	00	Fixed bit pattern
11:10	opcode	2-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: Instruction

Variants

Variant	Mnemonic Example	Description
Default	Instruction

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

Required Features

---

SQDMULH_SCALAR

ARM64 SQDMULH_SCALAR instruction

Encoding

Bits	Field	Description
31:30	01	Fixed bit pattern
29	U	1-bit value (0=signed, 1=unsigned)
28:24	11110	Fixed bit pattern
23:22	size	2-bit value (element size)
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:10	101101	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: MUL, MULS

Variants

Variant	Mnemonic Example	Description
Default	MUL

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

SQDMULL_SCALAR

ARM64 SQDMULL_SCALAR instruction

Encoding

Bits	Field	Description
31:30	01	Fixed bit pattern
29	U	Fixed value: 0
28:24	11110	Fixed bit pattern
23:22	size	2-bit value (element size)
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:12	opcode	4-bit value
11:10	00	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: MUL, MULS

Variants

Variant	Mnemonic Example	Description
Default	MUL

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

SQRDMLAH_SCALAR

ARM64 SQRDMLAH_SCALAR instruction

Encoding

Bits	Field	Description
31:30	01	Fixed bit pattern
29	U	Fixed value: 1
28:24	11110	Fixed bit pattern
23:22	size	2-bit value (element size)
21	0	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:12	1000	Fixed bit pattern
11	S	1-bit value (0=don't set flags, 1=set flags)
10	1	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: SQRDMLH

Variants

Variant	Mnemonic Example	Description
Default	SQRDMLH

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

Required Features

RDM

---

SUBP

ARM64 SUBP instruction

Encoding

Bits	Field	Description
31	sf	Fixed value: 1
30	0	Fixed bit pattern
29	S	1-bit value (0=don't set flags, 1=set flags)
28:21	11010110	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:10	000000	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: SUB, SUBS

Variants

Variant	Mnemonic Example	Description
Default	SUB
Cmp	CMP	Compare variant (sets flags)

Default Operands:

Parameter	Type
Rd	General-purpose register
Rn	GP register or SP
Rm	GP register or SP

Cmp Operands:

Parameter	Type
Rd	Zero register
Rn	GP register or SP
Rm	GP register or SP

Required Features

MTE

---

SVC

ARM64 SVC instruction

Encoding

Bits	Field	Description
31:21	11010100000	Fixed bit pattern
20:5	imm16	16-bit value
4:2	000	Fixed bit pattern
1:0	LL	2-bit value

Mnemonic

Examples: C

Variants

Variant	Mnemonic Example	Description
Default	C

Default Operands:

Parameter	Type
imm16	Unsigned immediate

Required Features

---

SWP

ARM64 SWP instruction

Encoding

Bits	Field	Description
31:30	size	2-bit value (element size)
29:24	111000	Fixed bit pattern
23	A	1-bit value
22	R	1-bit value
21	1	Fixed bit pattern
20:16	Rs	5-bit value
15:10	100000	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: B, BL, BX

Variants

Variant	Mnemonic Example	Description
Default	B

Default Operands:

Parameter	Type
Rs	General-purpose register
Rt	General-purpose register
Rn	GP register or SP

Required Features

LSE

---

TAGINSERT

ARM64 TAGINSERT instruction

Encoding

Bits	Field	Description
31	sf	Fixed value: 1
30	0	Fixed bit pattern
29	S	Fixed value: 0
28:21	11010110	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:11	00010	Fixed bit pattern
10	op	1-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: Instruction

Variants

Variant	Mnemonic Example	Description
Default	Instruction

Default Operands:

Parameter	Type
Rd	General-purpose register
Rn	GP register or SP
Rm	General-purpose register

Required Features

MTE

---

TCANCEL

ARM64 TCANCEL instruction

Encoding

Bits	Field	Description
31:21	11010100011	Fixed bit pattern
20:5	imm16	16-bit value
4:0	00000	Fixed bit pattern

Mnemonic

Examples: TCANCEL

Variants

Variant	Mnemonic Example	Description
Default	TCANCEL

Default Operands:

Parameter	Type
imm16	Unsigned immediate

Required Features

TME

---

TCOMMIT

ARM64 TCOMMIT instruction

Encoding

Bits	Field	Description
31:0	11010101000000110011000001111111	Fixed bit pattern

Mnemonic

Examples: TCOMMIT

Variants

Variant	Mnemonic Example	Description
Default	TCOMMIT

---

TSTART

ARM64 TSTART instruction

Encoding

Bits	Field	Description
31:5	110101010010001100110000011	Fixed bit pattern
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: STR, STRB, STRH

Variants

Variant	Mnemonic Example	Description
Default	STR

Default Operands:

Parameter	Type
Rt	General-purpose register

Required Features

TME

---

TTEST

ARM64 TTEST instruction

Encoding

Bits	Field	Description
31:5	110101010010001100110001011	Fixed bit pattern
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: STR, STRB, STRH

Variants

Variant	Mnemonic Example	Description
Default	STR

Default Operands:

Parameter	Type
Rt	General-purpose register

Required Features

TME

---

UDF

ARM64 UDF instruction

Encoding

Bits	Field	Description
31:16	0000000000000000	Fixed bit pattern
15:0	imm16	16-bit value

Mnemonic

Examples: UDF

Variants

Variant	Mnemonic Example	Description
Default	UDF

Default Operands:

Parameter	Type
imm16	Unsigned immediate

---

WFXT

ARM64 WFXT instruction

Encoding

Bits	Field	Description
31:8	110101010000001100010000	Fixed bit pattern
7:5	op2	3-bit value
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: WFT

Variants

Variant	Mnemonic Example	Description
Default	WFT

Default Operands:

Parameter	Type
Rd	General-purpose register

Required Features

WFxT

---

XPAC

ARM64 XPAC instruction

Encoding

Bits	Field	Description
31:11	110110101100000101000	Fixed bit pattern
10	D	1-bit value
9:5	Rn	Fixed value: 11111
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: PACIA, PACIB, PACDA, PACDB

Variants

Variant	Mnemonic Example	Description
Default	PACIA

Default Operands:

Parameter	Type
Rd	General-purpose register

Required Features

PAuth

---

XTN_SCALAR

ARM64 XTN_SCALAR instruction

Encoding

Bits	Field	Description
31:30	01	Fixed bit pattern
29	U	1-bit value (0=signed, 1=unsigned)
28:24	11110	Fixed bit pattern
23:22	size	2-bit value (element size)
21:15	1000010	Fixed bit pattern
14:13	op	2-bit value
12:10	010	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: Instruction

Variants

Variant	Mnemonic Example	Description
Default	Instruction

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

---

ZIP

ARM64 ZIP instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29:24	001110	Fixed bit pattern
23:22	size	2-bit value (element size)
21	0	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15	0	Fixed bit pattern
14:12	opcode	3-bit value
11:10	10	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: Instruction

Variants

Variant	Mnemonic Example	Description
Default	Instruction

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

Branches

Instruction	Description
BCOND	Branches instruction
BFM	Branches instruction
BIT_VEC	Branches instruction
BRANCH	Branches instruction
BRANCHREG	Branches instruction
BRK	Branches instruction
CBZ	Branches instruction
TBZ	Branches instruction

BCOND

ARM64 BCOND instruction

Encoding

Bits	Field	Description
31:24	01010100	Fixed bit pattern
23:5	imm19	19-bit value
4	C	1-bit value
3:0	bcond	4-bit value

Mnemonic

Examples: B, BL, BX

Variants

Variant	Mnemonic Example	Description
Default	B

Default Operands:

Parameter	Type
bcond	Condition code
imm19	Relative address

Required Features

---

BFM

ARM64 BFM instruction

Encoding

Bits	Field	Description
31	sf	1-bit value (0=32-bit, 1=64-bit)
30:29	opc	2-bit value
28:23	100110	Fixed bit pattern
22	N	1-bit value
21:16	immr	6-bit value
15:10	imms	6-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: B, BL, BX

Variants

Variant	Mnemonic Example	Description
Default	B
Sr	SRi
Sl	LSLi
Bfx	B	Bitfield extract variant
Bfi	B	Bitfield insert variant
Bfc	B
Extb	B
Exth	XTH
Extw	XTW

Default Operands:

Parameter	Type
Rd	General-purpose register
Rn	General-purpose register
immr	Immediate value
imms	Immediate value

Sr Operands:

Parameter	Type
Rd	General-purpose register
Rn	General-purpose register
immr	Immediate value
imms	Constant value

Sl Operands:

Parameter	Type
Rd	General-purpose register
Rn	General-purpose register
immr,imms	immlsl

Bfx Operands:

Parameter	Type
Rd	General-purpose register
Rn	General-purpose register
immr,imms	immbfx

Bfi Operands:

Parameter	Type
Rd	General-purpose register
Rn	General-purpose register
immr,imms	immbfi

Bfc Operands:

Parameter	Type
Rd	General-purpose register
Rn	Zero register
immr,imms	immbfi

Extb Operands:

Parameter	Type
Rd	General-purpose register
Rn	General-purpose register
immr	Constant value
imms	Constant value

Exth Operands:

Parameter	Type
Rd	General-purpose register
Rn	General-purpose register
immr	Constant value
imms	Constant value

Extw Operands:

Parameter	Type
Rd	General-purpose register
Rn	General-purpose register
immr	Constant value
imms	Constant value

---

BIT_VEC

ARM64 BIT_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23:22	op	2-bit value
21:10	100000010110	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: B, BL, BX

Variants

Variant	Mnemonic Example	Description
Default	B
Mvn	Instruction	Move Not variant (inverted move)

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

Mvn Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

---

BRANCH

ARM64 BRANCH instruction

Encoding

Bits	Field	Description
31	op	1-bit value
30:26	00101	Fixed bit pattern
25:0	imm26	26-bit value

Mnemonic

Examples: B, BL, BX

Variants

Variant	Mnemonic Example	Description
Default	B

Default Operands:

Parameter	Type
imm26	Relative address

---

BRANCHREG

ARM64 BRANCHREG instruction

Encoding

Bits	Field	Description
31:25	1101011	Fixed bit pattern
24	Z	1-bit value
23	0	Fixed bit pattern
22:21	op	2-bit value
20:12	111110000	Fixed bit pattern
11	A	1-bit value
10	M	1-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rm	5-bit value (second source register)

Mnemonic

Examples: B, BL, BX

Variants

Variant	Mnemonic Example	Description
Default	B

Default Operands:

Parameter	Type
Rn
Rm

Required Features

---

BRK

ARM64 BRK instruction

Encoding

Bits	Field	Description
31:21	11010100001	Fixed bit pattern
20:5	imm16	16-bit value
4:0	00000	Fixed bit pattern

Mnemonic

Examples: B, BL, BX

Variants

Variant	Mnemonic Example	Description
Default	B

Default Operands:

Parameter	Type
imm16	Unsigned immediate

---

CBZ

ARM64 CBZ instruction

Encoding

Bits	Field	Description
31	sf	1-bit value (0=32-bit, 1=64-bit)
30:25	011010	Fixed bit pattern
24	op	1-bit value
23:5	imm19	19-bit value
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: B, BL, BX

Variants

Variant	Mnemonic Example	Description
Default	B

Default Operands:

Parameter	Type
Rt	General-purpose register
imm19	Relative address

---

TBZ

ARM64 TBZ instruction

Encoding

Bits	Field	Description
31	b5	1-bit value
30:25	011011	Fixed bit pattern
24	op	1-bit value
23:19	b40	5-bit value
18:5	imm14	14-bit value
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: B, BL, BX

Variants

Variant	Mnemonic Example	Description
Default	B

Default Operands:

Parameter	Type
Rt	General-purpose register
b5,b40	tbz
imm14	Relative address

---

Loads and Stores

Instruction	Description
LDATOMIC	Loads and Stores instruction
LDG	Loads and Stores instruction
LDRAUT	Loads and Stores instruction
MEMGM	Loads and Stores instruction
MEMNP	Loads and Stores instruction
MEMOR	Loads and Stores instruction
MEMP	Loads and Stores instruction
MEMP_FP	Loads and Stores instruction
MEMSIMD_MULT	Loads and Stores instruction
MEMSIMDMULTPOST	Loads and Stores instruction
MEMSIMD_REP	Loads and Stores instruction
MEMSIMDREPPOST	Loads and Stores instruction
MEMSIMD_SINGLE	Loads and Stores instruction
MEMSIMDSINGLEPOST	Loads and Stores instruction
MEMU	Loads and Stores instruction
MEMU_FP	Loads and Stores instruction
MEMX	Loads and Stores instruction
MEM_IMM	Loads and Stores instruction
MEMIMMFP	Loads and Stores instruction
MEM_LIT	Loads and Stores instruction
MEMLITFP	Loads and Stores instruction
MEM_REG	Loads and Stores instruction
MEMREGFP	Loads and Stores instruction
STG	Loads and Stores instruction

LDATOMIC

ARM64 LDATOMIC instruction

Encoding

Bits	Field	Description
31:30	size	2-bit value (element size)
29:27	111	Fixed bit pattern
26	VR	Fixed value: 0
25:24	00	Fixed bit pattern
23	A	1-bit value
22	R	1-bit value
21	1	Fixed bit pattern
20:16	Rs	5-bit value
15	o3	Fixed value: 0
14:12	opc	3-bit value
11:10	00	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: ADD, ADDS

Variants

Variant	Mnemonic Example	Description
Default	ADD

Default Operands:

Parameter	Type
Rs	General-purpose register
Rt	General-purpose register
Rn	GP register or SP

Required Features

LSE

---

LDG

ARM64 LDG instruction

Encoding

Bits	Field	Description
31:24	11011001	Fixed bit pattern
23:22	opc	Fixed value: 01
21	1	Fixed bit pattern
20:12	imm9	9-bit value
11:10	op2	Fixed value: 00
9:5	Rn	5-bit value (first source register)
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: LDR, LDRB, LDRH

Variants

Variant	Mnemonic Example	Description
Default	ldg

Default Operands:

Parameter	Type
Rt	General-purpose register
Rn	GP register or SP
imm9	Signed immediate

Required Features

MTE

---

LDRAUT

ARM64 LDRAUT instruction

Encoding

Bits	Field	Description
31:30	size	Fixed value: 11
29:24	111000	Fixed bit pattern
23	M	1-bit value
22	S	1-bit value (0=don't set flags, 1=set flags)
21	1	Fixed bit pattern
20:12	imm9	9-bit value
11	W	1-bit value
10	1	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: LDR, LDRB, LDRH

Variants

Variant	Mnemonic Example	Description
Default	LDR

Default Operands:

Parameter	Type
Rt	General-purpose register
Rn	GP register or SP
S,imm9	immldraut

Required Features

PAuth

---

MEMGM

ARM64 MEMGM instruction

Encoding

Bits	Field	Description
31:24	11011001	Fixed bit pattern
23:22	opc	2-bit value
21:10	100000000000	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: LDR, LDRB, LDRH

Variants

Variant	Mnemonic Example	Description
Default	LDR

Default Operands:

Parameter	Type
Rt	General-purpose register
Rn	GP register or SP

Required Features

`MTE2

This is MSR_IMM`

---

MEMNP

ARM64 MEMNP instruction

Encoding

Bits	Field	Description
31:30	opc	2-bit value
29:23	1010000	Fixed bit pattern
22	L	1-bit value
21:15	imm7	7-bit value
14:10	Rt2	5-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: LDR, LDRB, LDRH

Variants

Variant	Mnemonic Example	Description
Default	LDR

Default Operands:

Parameter	Type
Rt	General-purpose register
Rt2	General-purpose register
Rn	GP register or SP
imm7	Signed immediate

---

MEMOR

ARM64 MEMOR instruction

Encoding

Bits	Field	Description
31:30	size	2-bit value (element size)
29:23	0010001	Fixed bit pattern
22	L	1-bit value
21	0	Fixed bit pattern
20:16	Rs	5-bit value
15	o0	1-bit value
14:10	Rt2	5-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: LDR, LDRB, LDRH

Variants

Variant	Mnemonic Example	Description
Default	LDR

Default Operands:

Parameter	Type
Rs	Zero register
Rt	General-purpose register
Rt2	Zero register
Rn	GP register or SP

Required Features

---

MEMP

ARM64 MEMP instruction

Encoding

Bits	Field	Description
31:30	opc	2-bit value
29:25	10100	Fixed bit pattern
24:23	op2	2-bit value
22	L	1-bit value
21:15	imm7	7-bit value
14:10	Rt2	5-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: LDR, LDRB, LDRH

Variants

Variant	Mnemonic Example	Description
Default	LDR

Default Operands:

Parameter	Type
Rt	General-purpose register
Rt2	General-purpose register
Rn	GP register or SP
imm7	Signed immediate

Required Features

---

MEMP_FP

ARM64 MEMP_FP instruction

Encoding

Bits	Field	Description
31:30	opc	2-bit value
29:27	101	Fixed bit pattern
26	V	Fixed value: 1
25	0	Fixed bit pattern
24:23	op2	2-bit value
22	L	1-bit value
21:15	imm7	7-bit value
14:10	Rt2	5-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: LDR, LDRB, LDRH

Variants

Variant	Mnemonic Example	Description
Default	LDR

Default Operands:

Parameter	Type
Rt	Floating-point register
Rt2	Floating-point register
Rn	GP register or SP
imm7	Signed immediate

---

MEMSIMD_MULT

ARM64 MEMSIMD_MULT instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29:23	0011000	Fixed bit pattern
22	L	1-bit value
21:16	000000	Fixed bit pattern
15:12	opcode	4-bit value
11:10	size	2-bit value (element size)
9:5	Rn	5-bit value (first source register)
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: LDR, LDRB, LDRH

Variants

Variant	Mnemonic Example	Description
Default	LDR

Default Operands:

Parameter	Type
Rt	Floating-point register
Rn	GP register or SP

---

MEMSIMDMULTPOST

ARM64 MEMSIMDMULTPOST instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29:23	0011001	Fixed bit pattern
22	L	1-bit value
21	0	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:12	opcode	4-bit value
11:10	size	2-bit value (element size)
9:5	Rn	5-bit value (first source register)
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: LDR, LDRB, LDRH

Variants

Variant	Mnemonic Example	Description
Default	LDR
Noreg	LDR

Default Operands:

Parameter	Type
Rt	Floating-point register
Rn	GP register or SP
Rm	reggpnozr

Noreg Operands:

Parameter	Type
Rt	Floating-point register
Rn	GP register or SP
Rm	Zero register

---

MEMSIMD_REP

ARM64 MEMSIMD_REP instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29:23	0011010	Fixed bit pattern
22	L	Fixed value: 1
21	R	1-bit value
20:16	00000	Fixed bit pattern
15:13	opc	3-bit value
12	S	Fixed value: 0
11:10	size	2-bit value (element size)
9:5	Rn	5-bit value (first source register)
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: LDR, LDRB, LDRH

Variants

Variant	Mnemonic Example	Description
Default	LDR

Default Operands:

Parameter	Type
Rt	Floating-point register
Rn	GP register or SP

---

MEMSIMDREPPOST

ARM64 MEMSIMDREPPOST instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29:23	0011011	Fixed bit pattern
22	L	Fixed value: 1
21	R	1-bit value
20:16	Rm	5-bit value (second source register)
15:13	opc	3-bit value
12	S	Fixed value: 0
11:10	size	2-bit value (element size)
9:5	Rn	5-bit value (first source register)
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: LDR, LDRB, LDRH

Variants

Variant	Mnemonic Example	Description
Default	LDR
Noreg	LDR

Default Operands:

Parameter	Type
Rt	Floating-point register
Rn	GP register or SP
Rm	reggpnozr

Noreg Operands:

Parameter	Type
Rt	Floating-point register
Rn	GP register or SP
Rm	Zero register

---

MEMSIMD_SINGLE

ARM64 MEMSIMD_SINGLE instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29:23	0011010	Fixed bit pattern
22	L	1-bit value
21	R	1-bit value
20:16	00000	Fixed bit pattern
15:13	opc	3-bit value
12	S	1-bit value (0=don't set flags, 1=set flags)
11:10	size	2-bit value (element size)
9:5	Rn	5-bit value (first source register)
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: LDR, LDRB, LDRH

Variants

Variant	Mnemonic Example	Description
Default	LDR

Default Operands:

Parameter	Type
Rt	Floating-point register
Q,S,size	memsimdidx
Rn	GP register or SP

---

MEMSIMDSINGLEPOST

ARM64 MEMSIMDSINGLEPOST instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29:23	0011011	Fixed bit pattern
22	L	1-bit value
21	R	1-bit value
20:16	Rm	5-bit value (second source register)
15:13	opc	3-bit value
12	S	1-bit value (0=don't set flags, 1=set flags)
11:10	size	2-bit value (element size)
9:5	Rn	5-bit value (first source register)
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: LDR, LDRB, LDRH

Variants

Variant	Mnemonic Example	Description
Default	LDR
Noreg	LDR

Default Operands:

Parameter	Type
Rt	Floating-point register
Q,S,size	memsimdidx
Rn	GP register or SP
Rm	reggpnozr

Noreg Operands:

Parameter	Type
Rt	Floating-point register
Q,S,size	memsimdidx
Rn	GP register or SP
Rm	Zero register

---

MEMU

ARM64 MEMU instruction

Encoding

Bits	Field	Description
31:30	size	2-bit value (element size)
29:24	111000	Fixed bit pattern
23:22	opc	2-bit value
21	0	Fixed bit pattern
20:12	imm9	9-bit value
11:10	op2	2-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: LDR, LDRB, LDRH

Variants

Variant	Mnemonic Example	Description
Default	LDR

Default Operands:

Parameter	Type
Rt
Rn	GP register or SP
imm9	Signed immediate

---

MEMU_FP

ARM64 MEMU_FP instruction

Encoding

Bits	Field	Description
31:30	size	2-bit value (element size)
29:27	111	Fixed bit pattern
26	V	Fixed value: 1
25:24	00	Fixed bit pattern
23:22	opc	2-bit value
21	0	Fixed bit pattern
20:12	imm9	9-bit value
11:10	op4	2-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: LDR, LDRB, LDRH

Variants

Variant	Mnemonic Example	Description
Default	LDR

Default Operands:

Parameter	Type
Rt	Floating-point register
Rn	GP register or SP
imm9	Signed immediate

---

MEMX

ARM64 MEMX instruction

Encoding

Bits	Field	Description
31:30	size	2-bit value (element size)
29:23	0010000	Fixed bit pattern
22	L	1-bit value
21	P	1-bit value
20:16	Rs	5-bit value
15	o0	1-bit value
14:10	Rt2	5-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: LDR, LDRB, LDRH

Variants

Variant	Mnemonic Example	Description
Default	LDR

Default Operands:

Parameter	Type
Rs
Rt	General-purpose register
Rt2
Rn	GP register or SP

---

MEM_IMM

ARM64 MEM_IMM instruction

Encoding

Bits	Field	Description
31:30	size	2-bit value (element size)
29:24	111001	Fixed bit pattern
23:22	opc	2-bit value
21:10	imm12	12-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: LDR, LDRB, LDRH

Variants

Variant	Mnemonic Example	Description
Default	LDR

Default Operands:

Parameter	Type
Rt
Rn	GP register or SP
imm12	Unsigned immediate

---

MEMIMMFP

ARM64 MEMIMMFP instruction

Encoding

Bits	Field	Description
31:30	size	2-bit value (element size)
29:27	111	Fixed bit pattern
26	V	Fixed value: 1
25:24	01	Fixed bit pattern
23:22	opc	2-bit value
21:10	imm12	12-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: LDR, LDRB, LDRH

Variants

Variant	Mnemonic Example	Description
Default	LDR

Default Operands:

Parameter	Type
Rt	Floating-point register
Rn	GP register or SP
imm12	Unsigned immediate

---

MEM_LIT

ARM64 MEM_LIT instruction

Encoding

Bits	Field	Description
31:30	opc	2-bit value
29:24	011000	Fixed bit pattern
23:5	imm19	19-bit value
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: LDR, LDRB, LDRH

Variants

Variant	Mnemonic Example	Description
Default	LDR

Default Operands:

Parameter	Type
Rt
imm19	Relative address

---

MEMLITFP

ARM64 MEMLITFP instruction

Encoding

Bits	Field	Description
31:30	opc	2-bit value
29:27	011	Fixed bit pattern
26	V	Fixed value: 1
25:24	00	Fixed bit pattern
23:5	imm19	19-bit value
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: LDR, LDRB, LDRH

Variants

Variant	Mnemonic Example	Description
Default	LDR

Default Operands:

Parameter	Type
Rt	Floating-point register
imm19	Relative address

---

MEM_REG

ARM64 MEM_REG instruction

Encoding

Bits	Field	Description
31:30	size	2-bit value (element size)
29:24	111000	Fixed bit pattern
23:22	opc	2-bit value
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:13	option	3-bit value
12	sc	1-bit value
11:10	10	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: LDR, LDRB, LDRH

Variants

Variant	Mnemonic Example	Description
Default	LDR
Noext	LDR

Default Operands:

Parameter	Type
Rt
Rn	GP register or SP
Rm	General-purpose register
sc	bool

Noext Operands:

Parameter	Type
Rt
Rn	GP register or SP
Rm	General-purpose register

---

MEMREGFP

ARM64 MEMREGFP instruction

Encoding

Bits	Field	Description
31:30	size	2-bit value (element size)
29:27	111	Fixed bit pattern
26	V	Fixed value: 1
25:24	00	Fixed bit pattern
23:22	opc	2-bit value
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:13	option	3-bit value
12	sc	1-bit value
11:10	10	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: LDR, LDRB, LDRH

Variants

Variant	Mnemonic Example	Description
Default	LDR
Noext	LDR

Default Operands:

Parameter	Type
Rt	Floating-point register
Rn	GP register or SP
Rm	General-purpose register
sc	bool

Noext Operands:

Parameter	Type
Rt	Floating-point register
Rn	GP register or SP
Rm	General-purpose register

---

STG

ARM64 STG instruction

Encoding

Bits	Field	Description
31:24	11011001	Fixed bit pattern
23:22	opc	2-bit value
21	1	Fixed bit pattern
20:12	imm9	9-bit value
11:10	op2	2-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: STR, STRB, STRH

Variants

Variant	Mnemonic Example	Description
Default	STR

Default Operands:

Parameter	Type
Rt	GP register or SP
Rn	GP register or SP
imm9	Signed immediate

Required Features

MTE

---

SIMD and Vector

Instruction	Description
ABDL_VEC	SIMD and Vector instruction
ABD_VEC	SIMD and Vector instruction
ADDLP_VEC	SIMD and Vector instruction
ADDP_VEC	SIMD and Vector instruction
ADDSUBHN_VEC	SIMD and Vector instruction
ADDSUBL_VEC	SIMD and Vector instruction
ADDSUBW_VEC	SIMD and Vector instruction
ADDSUB_VEC	SIMD and Vector instruction
ANDOREOR_VEC	SIMD and Vector instruction
ARITH1_VEC	SIMD and Vector instruction
CLZ_VEC	SIMD and Vector instruction
CMEQ_VEC	SIMD and Vector instruction
CMGT_VEC	SIMD and Vector instruction
CMZERO_VEC	SIMD and Vector instruction
DOT_VEC	SIMD and Vector instruction
DUP_VEC	SIMD and Vector instruction
EXT	SIMD and Vector instruction
HADDSUB_VEC	SIMD and Vector instruction
INTHORZVEC	SIMD and Vector instruction
MINMAX_VEC	SIMD and Vector instruction
MULL_VEC	SIMD and Vector instruction
MUL_VEC	SIMD and Vector instruction
PMULL_VEC	SIMD and Vector instruction
QADDSUB_VEC	SIMD and Vector instruction
QSHLVECIMM	SIMD and Vector instruction
REV_VEC	SIMD and Vector instruction
SHIFTVECIMM	SIMD and Vector instruction
SHLLVECESZ	SIMD and Vector instruction
SHLLVECIMM	SIMD and Vector instruction
SHLREGVEC	SIMD and Vector instruction
SHRNVECIMM	SIMD and Vector instruction
SHRVECIMM	SIMD and Vector instruction
SIMD_IMM	SIMD and Vector instruction
SQDMULH_VEC	SIMD and Vector instruction
SQDMULL_VEC	SIMD and Vector instruction
SQRDMLAH_VEC	SIMD and Vector instruction
TBL	SIMD and Vector instruction
XTN_VEC	SIMD and Vector instruction

ABDL_VEC

ARM64 ABDL_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23:22	size	2-bit value (element size)
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:12	opcode	4-bit value
11:10	00	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: SABD, UABD, SABA, UABA

Variants

Variant	Mnemonic Example	Description
Default	SABD

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

ABD_VEC

ARM64 ABD_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23:22	size	2-bit value (element size)
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:12	0111	Fixed bit pattern
11	ac	1-bit value
10	1	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: B, BL, BX

Variants

Variant	Mnemonic Example	Description
Default	B

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

ADDLP_VEC

ARM64 ADDLP_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23:22	size	2-bit value (element size)
21:15	1000000	Fixed bit pattern
14	op	1-bit value
13:10	1010	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: ADLP

Variants

Variant	Mnemonic Example	Description
Default	ADLP

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

---

ADDP_VEC

ARM64 ADDP_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	Fixed value: 0
28:24	01110	Fixed bit pattern
23:22	size	2-bit value (element size)
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:10	101111	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: ADD, ADDS

Variants

Variant	Mnemonic Example	Description
Default	ADD

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

ADDSUBHN_VEC

ARM64 ADDSUBHN_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23:22	size	2-bit value (element size)
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:12	opcode	4-bit value
11:10	00	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: ADD, ADDS

Variants

Variant	Mnemonic Example	Description
Default	ADD

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

ADDSUBL_VEC

ARM64 ADDSUBL_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23:22	size	2-bit value (element size)
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:12	opcode	4-bit value
11:10	00	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: ADD, ADDS

Variants

Variant	Mnemonic Example	Description
Default	ADD

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

ADDSUBW_VEC

ARM64 ADDSUBW_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23:22	size	2-bit value (element size)
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:12	opcode	4-bit value
11:10	00	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: ADD, ADDS

Variants

Variant	Mnemonic Example	Description
Default	ADD

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

ADDSUB_VEC

ARM64 ADDSUB_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23:22	size	2-bit value (element size)
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:10	100001	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: ADD, ADDS

Variants

Variant	Mnemonic Example	Description
Default	ADD

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

ANDOREOR_VEC

ARM64 ANDOREOR_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23:22	size	2-bit value (element size)
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:10	000111	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: AND, ANDS

Variants

Variant	Mnemonic Example	Description
Default	AND
Mov	MOV	Move variant (simplified form)

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

Mov Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	@Rn

---

ARITH1_VEC

ARM64 ARITH1_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23:22	size	2-bit value (element size)
21:16	100000	Fixed bit pattern
15:14	op	2-bit value
13:10	1110	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: ADD, ADDS

Variants

Variant	Mnemonic Example	Description
Default	ADD

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

---

CLZ_VEC

ARM64 CLZ_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23:22	size	2-bit value (element size)
21:10	100000010010	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: CL

Variants

Variant	Mnemonic Example	Description
Default	CL

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

---

CMEQ_VEC

ARM64 CMEQ_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23:22	size	2-bit value (element size)
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:10	100011	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: STR, STRB, STRH

Variants

Variant	Mnemonic Example	Description
Default	STR

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

CMGT_VEC

ARM64 CMGT_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23:22	size	2-bit value (element size)
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:12	0011	Fixed bit pattern
11	eq	1-bit value
10	1	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: CMV

Variants

Variant	Mnemonic Example	Description
Default	CM

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

CMZERO_VEC

ARM64 CMZERO_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23:22	size	2-bit value (element size)
21:14	10000010	Fixed bit pattern
13:12	op	2-bit value
11:10	10	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: CM

Variants

Variant	Mnemonic Example	Description
Default	CM

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

---

DOT_VEC

ARM64 DOT_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23:22	size	2-bit value (element size)
21	0	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15	1	Fixed bit pattern
14:11	opcode	4-bit value
10	1	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: B, BL, BX

Variants

Variant	Mnemonic Example	Description
Default	B

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

Required Features

---

DUP_VEC

ARM64 DUP_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29:21	001110000	Fixed bit pattern
20:16	imm5	5-bit value
15:12	0000	Fixed bit pattern
11	op	1-bit value
10	1	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)
-1:-4	0000	Fixed bit pattern
-5:-8	1000	Fixed bit pattern
-9	0	Fixed bit pattern

Mnemonic

Examples: DUP

Variants

Variant	Mnemonic Example	Description
Elem	DUP
Gp	DUP

Elem Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
imm5	immvidx

Gp Operands:

Parameter	Type
Rd	Floating-point register
Rn	General-purpose register

---

EXT

ARM64 EXT instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29:24	101110	Fixed bit pattern
23:22	size	Fixed value: 00
21	0	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15	0	Fixed bit pattern
14:11	imm4	4-bit value
10	0	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: EXT

Variants

Variant	Mnemonic Example	Description
Default	EXT

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register
imm4	Immediate value

---

HADDSUB_VEC

ARM64 HADDSUB_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23:22	size	2-bit value (element size)
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:14	00	Fixed bit pattern
13	op	1-bit value
12	R	1-bit value
11:10	01	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: ADD, ADDS

Variants

Variant	Mnemonic Example	Description
Default	ADD

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

INTHORZVEC

ARM64 INTHORZVEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23:22	size	2-bit value (element size)
21:17	11000	Fixed bit pattern
16:12	opcode	5-bit value
11:10	10	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: ADD, ADDS

Variants

Variant	Mnemonic Example	Description
Default	ADD

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

---

MINMAX_VEC

ARM64 MINMAX_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23:22	size	2-bit value (element size)
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:14	o2	2-bit value
13:12	10	Fixed bit pattern
11	o1	1-bit value
10	1	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: Instruction

Variants

Variant	Mnemonic Example	Description
Default	Instruction

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

MULL_VEC

ARM64 MULL_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23:22	size	2-bit value (element size)
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:12	opcode	4-bit value
11:10	00	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: MUL, MULS

Variants

Variant	Mnemonic Example	Description
Default	MUL

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

MUL_VEC

ARM64 MUL_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23:22	size	2-bit value (element size)
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:12	1001	Fixed bit pattern
11	ac	1-bit value
10	1	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)
-1:-2	11	Fixed bit pattern
-3:-4	00	Fixed bit pattern

Mnemonic

Examples: MUL, MULS

Variants

Variant	Mnemonic Example	Description
Default	MUL

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

PMULL_VEC

ARM64 PMULL_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	Fixed value: 0
28:24	01110	Fixed bit pattern
23:22	size	2-bit value (element size)
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:12	opcode	Fixed value: 1110
11:10	00	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: MUL, MULS

Variants

Variant	Mnemonic Example	Description
Default	MUL

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

Required Features

---

QADDSUB_VEC

ARM64 QADDSUB_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23:22	size	2-bit value (element size)
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:14	00	Fixed bit pattern
13	op	1-bit value
12:10	011	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: ADD, ADDS

Variants

Variant	Mnemonic Example	Description
Default	ADD

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

QSHLVECIMM

ARM64 QSHLVECIMM instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:23	011110	Fixed bit pattern
22:19	immh	4-bit value
18:16	immb	3-bit value
15:13	011	Fixed bit pattern
12	op	1-bit value
11:10	01	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)
-1	0	Fixed bit pattern

Mnemonic

Examples: Instruction

Variants

Variant	Mnemonic Example	Description
Default	i

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
immh,immb	immshiftl

---

REV_VEC

ARM64 REV_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23:22	size	2-bit value (element size)
21:13	100000000	Fixed bit pattern
12	op	1-bit value
11:10	10	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)
-1	1	Fixed bit pattern
-2	0	Fixed bit pattern
-3	1	Fixed bit pattern

Mnemonic

Examples: REV, REV16, RBIT

Variants

Variant	Mnemonic Example	Description
Default	REV

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

---

SHIFTVECIMM

ARM64 SHIFTVECIMM instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:23	011110	Fixed bit pattern
22:19	immh	4-bit value
18:16	immb	3-bit value
15:13	010	Fixed bit pattern
12	op	1-bit value
11:10	01	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)
-1	0	Fixed bit pattern

Mnemonic

Examples: Instruction

Variants

Variant	Mnemonic Example	Description
Default	i

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
immh,immb	immshift

---

SHLLVECESZ

ARM64 SHLLVECESZ instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	Fixed value: 1
28:24	01110	Fixed bit pattern
23:22	size	2-bit value (element size)
21:10	100001001110	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: SHLL

Variants

Variant	Mnemonic Example	Description
Default	SHLL

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

---

SHLLVECIMM

ARM64 SHLLVECIMM instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:23	011110	Fixed bit pattern
22:19	immh	4-bit value
18:16	immb	3-bit value
15:10	101001	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)
-1	0	Fixed bit pattern
-2	0	Fixed bit pattern

Mnemonic

Examples: SHLL

Variants

Variant	Mnemonic Example	Description
Default	SHLL
Xtl	XTL

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
immh,immb	immshiftl

Xtl Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
immb	Constant value

---

SHLREGVEC

ARM64 SHLREGVEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23:22	size	2-bit value (element size)
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:13	010	Fixed bit pattern
12	R	1-bit value
11	S	1-bit value (0=don't set flags, 1=set flags)
10	1	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: SHL

Variants

Variant	Mnemonic Example	Description
Default	SHL

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

SHRNVECIMM

ARM64 SHRNVECIMM instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:23	011110	Fixed bit pattern
22:19	immh	4-bit value
18:16	immb	3-bit value
15:13	100	Fixed bit pattern
12	op	1-bit value
11	R	1-bit value
10	1	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)
-1	0	Fixed bit pattern

Mnemonic

Examples: SHRN

Variants

Variant	Mnemonic Example	Description
Default	SHRNi

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
immh,immb	immshiftr

---

SHRVECIMM

ARM64 SHRVECIMM instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:23	011110	Fixed bit pattern
22:19	immh	4-bit value
18:16	immb	3-bit value
15:14	00	Fixed bit pattern
13	o1	1-bit value
12	o0	1-bit value
11:10	01	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)
-1	0	Fixed bit pattern

Mnemonic

Examples: Instruction

Variants

Variant	Mnemonic Example	Description
Default	i

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
immh,immb	immshiftr

---

SIMD_IMM

ARM64 SIMD_IMM instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	op	1-bit value
28:19	0111100000	Fixed bit pattern
18:16	immh	3-bit value
15:12	cmode	4-bit value
11	o2	1-bit value
10	1	Fixed bit pattern
9:5	imml	5-bit value
4:0	Rd	5-bit value (destination register)
-1	1	Fixed bit pattern

Mnemonic

Examples: ORR, ORRS

Variants

Variant	Mnemonic Example	Description
Movi	MOV
Bit32	ORR
Bit16	ORR
Fmov	MOV

Movi Operands:

Parameter	Type
Rd	Floating-point register
immh,imml,op,cmode	immsimd8movi

Bit32 Operands:

Parameter	Type
Rd	Floating-point register
immh,imml,cmode	immsimd8lsl

Bit16 Operands:

Parameter	Type
Rd	Floating-point register
immh,imml,cmode	immsimd8lsl

Fmov Operands:

Parameter	Type
Rd	Floating-point register
immh,imml	immsimd8fmov

Required Features

---

SQDMULH_VEC

ARM64 SQDMULH_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23:22	size	2-bit value (element size)
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:10	101101	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: MUL, MULS

Variants

Variant	Mnemonic Example	Description
Default	MUL

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

SQDMULL_VEC

ARM64 SQDMULL_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	Fixed value: 0
28:24	01110	Fixed bit pattern
23:22	size	2-bit value (element size)
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:12	opcode	4-bit value
11:10	00	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: MUL, MULS

Variants

Variant	Mnemonic Example	Description
Default	MUL

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

SQRDMLAH_VEC

ARM64 SQRDMLAH_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	Fixed value: 1
28:24	01110	Fixed bit pattern
23:22	size	2-bit value (element size)
21	0	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:12	1000	Fixed bit pattern
11	S	1-bit value (0=don't set flags, 1=set flags)
10	1	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: SQRDMLH

Variants

Variant	Mnemonic Example	Description
Default	SQRDMLH

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

Required Features

RDM

---

TBL

ARM64 TBL instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29:24	001110	Fixed bit pattern
23:22	size	Fixed value: 00
21	0	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15	0	Fixed bit pattern
14:13	len	2-bit value
12	op	1-bit value
11:10	00	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: B, BL, BX

Variants

Variant	Mnemonic Example	Description
Default	B

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

XTN_VEC

ARM64 XTN_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23:22	size	2-bit value (element size)
21:15	1000010	Fixed bit pattern
14:13	op	2-bit value
12:10	010	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: Instruction

Variants

Variant	Mnemonic Example	Description
Default	Instruction

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

---

Floating Point

Instruction	Description
FABD_SCALAR	Floating Point instruction
FADDSUB_VEC	Floating Point instruction
FARITH1	Floating Point instruction
FARITH1_VEC	Floating Point instruction
FARITH2	Floating Point instruction
FCCMP	Floating Point instruction
FCMLA_ELEM	Floating Point instruction
FCMLA_VEC	Floating Point instruction
FCMP	Floating Point instruction
FCMPREGSCALAR	Floating Point instruction
FCMPREGVEC	Floating Point instruction
FCMPZEROSCALAR	Floating Point instruction
FCMPZEROVEC	Floating Point instruction
FCSEL	Floating Point instruction
FCVTL_VEC	Floating Point instruction
FCVTN_SCALAR	Floating Point instruction
FCVTN_VEC	Floating Point instruction
FCVT_FP	Floating Point instruction
FCVT_FROMFIXED	Floating Point instruction
FCVT_FROMINT	Floating Point instruction
FCVTFROMINTSCALAR	Floating Point instruction
FCVTFROMINTVEC	Floating Point instruction
FCVT_SCALAR	Floating Point instruction
FCVTSCALARFIXED	Floating Point instruction
FCVT_TOFIXED	Floating Point instruction
FCVT_TOINT	Floating Point instruction
FCVT_VEC	Floating Point instruction
FCVTVECFIXED	Floating Point instruction
FDIV_VEC	Floating Point instruction
FHM_ELEM	Floating Point instruction
FHM_VEC	Floating Point instruction
FJCVTZS	Floating Point instruction
FMADD	Floating Point instruction
FMINMAX_VEC	Floating Point instruction
FMLAL_ELEM	Floating Point instruction
FMLAL_VEC	Floating Point instruction
FMLA_VEC	Floating Point instruction
FMOV_FROMGP	Floating Point instruction
FMOV_IMM	Floating Point instruction
FMOV_TOGP	Floating Point instruction
FMULX_SCALAR	Floating Point instruction
FMUL_ELEM	Floating Point instruction
FMULELEMFP16	Floating Point instruction
FMULELEMSCALAR	Floating Point instruction
FMULELEMSCALAR_FP16	Floating Point instruction
FMUL_VEC	Floating Point instruction
FP162REGSCALAR	Floating Point instruction
FP162REGVEC	Floating Point instruction
FP163REGSCALAR	Floating Point instruction
FP163REGVEC	Floating Point instruction
FPHORZSCALAR	Floating Point instruction
FPHORZVEC	Floating Point instruction
FRECP_SCALAR	Floating Point instruction
FRECPSTEPSCALAR	Floating Point instruction
FRECPSTEPVEC	Floating Point instruction
FRECP_VEC	Floating Point instruction
FRINT	Floating Point instruction
FRINTTS	Floating Point instruction
FRINTTS_VEC	Floating Point instruction
FRINT_VEC	Floating Point instruction

FABD_SCALAR

ARM64 FABD_SCALAR instruction

Encoding

Bits	Field	Description
31:30	01	Fixed bit pattern
29	U	Fixed value: 1
28:24	11110	Fixed bit pattern
23	o1	Fixed value: 1
22	sz	1-bit value
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:10	110101	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: SABD, UABD, SABA, UABA

Variants

Variant	Mnemonic Example	Description
Default	SABD

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

FADDSUB_VEC

ARM64 FADDSUB_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23	o1	1-bit value
22	sz	1-bit value
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:10	110101	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: ADD, ADDS

Variants

Variant	Mnemonic Example	Description
Default	ADD

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

FARITH1

ARM64 FARITH1 instruction

Encoding

Bits	Field	Description
31	M	Fixed value: 0
30	0	Fixed bit pattern
29	S	Fixed value: 0
28:24	11110	Fixed bit pattern
23:22	ftype	2-bit value
21:17	10000	Fixed bit pattern
16:15	opc	2-bit value
14:10	10000	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: MOV, MOVS, MVN

Variants

Variant	Mnemonic Example	Description
Default	MOV

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

Required Features

---

FARITH1_VEC

ARM64 FARITH1_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:23	011101	Fixed bit pattern
22	sz	1-bit value
21:17	10000	Fixed bit pattern
16	o1	1-bit value
15:10	111110	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: B, BL, BX

Variants

Variant	Mnemonic Example	Description
Default	B

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

---

FARITH2

ARM64 FARITH2 instruction

Encoding

Bits	Field	Description
31:24	00011110	Fixed bit pattern
23:22	ftype	2-bit value
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:12	opc	4-bit value
11:10	10	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: ADD, ADDS

Variants

Variant	Mnemonic Example	Description
Default	ADD

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

Required Features

---

FCCMP

ARM64 FCCMP instruction

Encoding

Bits	Field	Description
31:24	00011110	Fixed bit pattern
23:22	ftype	2-bit value
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:12	cond	4-bit value
11:10	01	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4	op	1-bit value
3:0	nzcv	4-bit value

Mnemonic

Examples: CMP, CMN

Variants

Variant	Mnemonic Example	Description
Default	CMP

Default Operands:

Parameter	Type
Rn	Floating-point register
Rm	Floating-point register
nzcv	Immediate value
cond	Condition code

Required Features

---

FCMLA_ELEM

ARM64 FCMLA_ELEM instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	Fixed value: 1
28:24	01111	Fixed bit pattern
23:22	size	2-bit value (element size)
21	L	1-bit value
20	M	1-bit value
19:16	Rm	4-bit value (second source register)
15	0	Fixed bit pattern
14:13	rot	2-bit value
12	1	Fixed bit pattern
11	H	1-bit value
10	0	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: FCMLA

Variants

Variant	Mnemonic Example	Description
Default	FCMLA

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
M,Rm	regfplim
H,L,M	velemidxlim
rot	immrotmul

Required Features

FCMA

---

FCMLA_VEC

ARM64 FCMLA_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	Fixed value: 1
28:24	01110	Fixed bit pattern
23:22	size	2-bit value (element size)
21	0	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:14	11	Fixed bit pattern
13	o1	1-bit value
12:11	rot	2-bit value
10	1	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: ADD, ADDS

Variants

Variant	Mnemonic Example	Description
Default	ADD

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register
rot	immrot

Required Features

FCMA

---

FCMP

ARM64 FCMP instruction

Encoding

Bits	Field	Description
31:24	00011110	Fixed bit pattern
23:22	ftype	2-bit value
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:10	001000	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:3	opc	2-bit value
2:0	000	Fixed bit pattern

Mnemonic

Examples: CMP, CMN

Variants

Variant	Mnemonic Example	Description
Default	CMP

Default Operands:

Parameter	Type
Rn	Floating-point register
Rm

Required Features

---

FCMPREGSCALAR

ARM64 FCMPREGSCALAR instruction

Encoding

Bits	Field	Description
31:30	01	Fixed bit pattern
29	U	1-bit value (0=signed, 1=unsigned)
28:24	11110	Fixed bit pattern
23	E	1-bit value
22	sz	1-bit value
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:12	1110	Fixed bit pattern
11	ac	1-bit value
10	1	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: F

Variants

Variant	Mnemonic Example	Description
Default	F

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

FCMPREGVEC

ARM64 FCMPREGVEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23	E	1-bit value
22	sz	1-bit value
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:12	1110	Fixed bit pattern
11	ac	1-bit value
10	1	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: F

Variants

Variant	Mnemonic Example	Description
Default	F

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

FCMPZEROSCALAR

ARM64 FCMPZEROSCALAR instruction

Encoding

Bits	Field	Description
31:30	01	Fixed bit pattern
29	U	1-bit value (0=signed, 1=unsigned)
28:23	111101	Fixed bit pattern
22	sz	1-bit value
21:14	10000011	Fixed bit pattern
13:12	op	2-bit value
11:10	10	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: FCM

Variants

Variant	Mnemonic Example	Description
Default	FCM

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

---

FCMPZEROVEC

ARM64 FCMPZEROVEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:23	011101	Fixed bit pattern
22	sz	1-bit value
21:14	10000011	Fixed bit pattern
13:12	op	2-bit value
11:10	10	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: FCM

Variants

Variant	Mnemonic Example	Description
Default	FCM

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

---

FCSEL

ARM64 FCSEL instruction

Encoding

Bits	Field	Description
31:24	00011110	Fixed bit pattern
23:22	ftype	2-bit value
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:12	cond	4-bit value
11:10	11	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: FCSEL

Variants

Variant	Mnemonic Example	Description
Default	FCSEL

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register
cond	Condition code

Required Features

---

FCVTL_VEC

ARM64 FCVTL_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	Fixed value: 0
28:23	011100	Fixed bit pattern
22	sz	1-bit value
21:10	100001011110	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: FCVTL

Variants

Variant	Mnemonic Example	Description
Default	FCVTL

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

---

FCVTN_SCALAR

ARM64 FCVTN_SCALAR instruction

Encoding

Bits	Field	Description
31:30	01	Fixed bit pattern
29	U	Fixed value: 1
28:23	111100	Fixed bit pattern
22	sz	Fixed value: 1
21:10	100001011010	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: FCVTXN

Variants

Variant	Mnemonic Example	Description
Default	FCVTXNs

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

---

FCVTN_VEC

ARM64 FCVTN_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23	o1	1-bit value
22	sz	1-bit value
21:10	100001011010	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: B, BL, BX

Variants

Variant	Mnemonic Example	Description
Default	B

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

Required Features

---

FCVT_FP

ARM64 FCVT_FP instruction

Encoding

Bits	Field	Description
31	M	Fixed value: 0
30	0	Fixed bit pattern
29	S	Fixed value: 0
28:24	11110	Fixed bit pattern
23:22	ftype	2-bit value
21:17	10001	Fixed bit pattern
16:15	opc	2-bit value
14:10	10000	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: B, BL, BX

Variants

Variant	Mnemonic Example	Description
Default	B

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

Required Features

---

FCVT_FROMFIXED

ARM64 FCVT_FROMFIXED instruction

Encoding

Bits	Field	Description
31	sf	1-bit value (0=32-bit, 1=64-bit)
30	0	Fixed bit pattern
29	S	Fixed value: 0
28:24	11110	Fixed bit pattern
23:22	ftype	2-bit value
21	0	Fixed bit pattern
20:19	rmode	Fixed value: 00
18:16	opcode	3-bit value
15:10	scale	6-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: CVTF

Variants

Variant	Mnemonic Example	Description
Default	CVTF

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	General-purpose register
scale	fcvtfixscale

Required Features

---

FCVT_FROMINT

ARM64 FCVT_FROMINT instruction

Encoding

Bits	Field	Description
31	sf	1-bit value (0=32-bit, 1=64-bit)
30	0	Fixed bit pattern
29	S	Fixed value: 0
28:24	11110	Fixed bit pattern
23:22	ftype	2-bit value
21	1	Fixed bit pattern
20:19	rmode	Fixed value: 00
18:16	opcode	3-bit value
15:10	000000	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: CVTF

Variants

Variant	Mnemonic Example	Description
Default	CVTF

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	General-purpose register

Required Features

---

FCVTFROMINTSCALAR

ARM64 FCVTFROMINTSCALAR instruction

Encoding

Bits	Field	Description
31:30	01	Fixed bit pattern
29	U	1-bit value (0=signed, 1=unsigned)
28:23	111100	Fixed bit pattern
22	sz	1-bit value
21:10	100001110110	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: CVTF

Variants

Variant	Mnemonic Example	Description
Default	CVTF

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

---

FCVTFROMINTVEC

ARM64 FCVTFROMINTVEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:23	011100	Fixed bit pattern
22	sz	1-bit value
21:10	100001110110	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: CVTF

Variants

Variant	Mnemonic Example	Description
Default	CVTF

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

---

FCVT_SCALAR

ARM64 FCVT_SCALAR instruction

Encoding

Bits	Field	Description
31:30	01	Fixed bit pattern
29	U	1-bit value (0=signed, 1=unsigned)
28:24	11110	Fixed bit pattern
23	o2	1-bit value
22	sz	1-bit value
21:17	10000	Fixed bit pattern
16:12	opcode	5-bit value
11:10	10	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: FCVT

Variants

Variant	Mnemonic Example	Description
Default	FCVT

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

---

FCVTSCALARFIXED

ARM64 FCVTSCALARFIXED instruction

Encoding

Bits	Field	Description
31:30	01	Fixed bit pattern
29	U	1-bit value (0=signed, 1=unsigned)
28:23	111110	Fixed bit pattern
22:19	immh	4-bit value
18:16	immb	3-bit value
15:13	111	Fixed bit pattern
12:11	op	2-bit value
10	1	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)
-1	0	Fixed bit pattern

Mnemonic

Examples: CVT

Variants

Variant	Mnemonic Example	Description
Default	CVTi

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
immh,immb	immshiftr

Required Features

---

FCVT_TOFIXED

ARM64 FCVT_TOFIXED instruction

Encoding

Bits	Field	Description
31	sf	1-bit value (0=32-bit, 1=64-bit)
30	0	Fixed bit pattern
29	S	Fixed value: 0
28:24	11110	Fixed bit pattern
23:22	ftype	2-bit value
21	0	Fixed bit pattern
20:19	rmode	Fixed value: 11
18:16	opcode	3-bit value
15:10	scale	6-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: FCVTZ

Variants

Variant	Mnemonic Example	Description
Default	FCVTZ

Default Operands:

Parameter	Type
Rd	General-purpose register
Rn	Floating-point register
scale	fcvtfixscale

Required Features

---

FCVT_TOINT

ARM64 FCVT_TOINT instruction

Encoding

Bits	Field	Description
31	sf	1-bit value (0=32-bit, 1=64-bit)
30	0	Fixed bit pattern
29	S	Fixed value: 0
28:24	11110	Fixed bit pattern
23:22	ftype	2-bit value
21	1	Fixed bit pattern
20:19	rmode	2-bit value
18:16	opcode	3-bit value
15:10	000000	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: FCVT

Variants

Variant	Mnemonic Example	Description
Default	FCVT

Default Operands:

Parameter	Type
Rd	General-purpose register
Rn	Floating-point register

Required Features

---

FCVT_VEC

ARM64 FCVT_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23	o2	1-bit value
22	sz	1-bit value
21:17	10000	Fixed bit pattern
16:12	opcode	5-bit value
11:10	10	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: FCVT

Variants

Variant	Mnemonic Example	Description
Default	FCVT

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

---

FCVTVECFIXED

ARM64 FCVTVECFIXED instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:23	011110	Fixed bit pattern
22:19	immh	4-bit value
18:16	immb	3-bit value
15:13	111	Fixed bit pattern
12:11	op	2-bit value
10	1	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)
-1	0	Fixed bit pattern

Mnemonic

Examples: CVT

Variants

Variant	Mnemonic Example	Description
Default	CVTi

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
immh,immb	immshiftr

Required Features

---

FDIV_VEC

ARM64 FDIV_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	Fixed value: 1
28:23	011100	Fixed bit pattern
22	sz	1-bit value
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:10	111111	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: SDIV, UDIV

Variants

Variant	Mnemonic Example	Description
Default	SDIV

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

FHM_ELEM

ARM64 FHM_ELEM instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01111	Fixed bit pattern
23:22	size	Fixed value: 10
21	L	1-bit value
20	M	1-bit value
19:16	Rm	4-bit value (second source register)
15	o1	1-bit value
14	S	1-bit value (0=don't set flags, 1=set flags)
13:12	00	Fixed bit pattern
11	H	1-bit value
10	0	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: FMLL

Variants

Variant	Mnemonic Example	Description
Default	FMLL

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
M,Rm	regfplim
H,L,M	velemidx

Required Features

FHM

---

FHM_VEC

ARM64 FHM_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23	S	1-bit value (0=don't set flags, 1=set flags)
22:21	01	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:11	opcode	5-bit value
10	1	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: FMLL

Variants

Variant	Mnemonic Example	Description
Default	FMLL

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

Required Features

FHM

---

FJCVTZS

ARM64 FJCVTZS instruction

Encoding

Bits	Field	Description
31	sf	Fixed value: 0
30	0	Fixed bit pattern
29	S	Fixed value: 0
28:24	11110	Fixed bit pattern
23:22	ftype	Fixed value: 01
21	1	Fixed bit pattern
20:19	rmode	Fixed value: 11
18:16	opcode	Fixed value: 110
15:10	000000	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: FJCVTZS

Variants

Variant	Mnemonic Example	Description
Default	FJCVTZSwd

Default Operands:

Parameter	Type
Rd	General-purpose register
Rn	Floating-point register

Required Features

JSCVT

---

FMADD

ARM64 FMADD instruction

Encoding

Bits	Field	Description
31:24	00011111	Fixed bit pattern
23:22	ftype	2-bit value
21	o1	1-bit value
20:16	Rm	5-bit value (second source register)
15	o0	1-bit value
14:10	Ra	5-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: ADD, ADDS

Variants

Variant	Mnemonic Example	Description
Default	ADD

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register
Ra	Floating-point register

Required Features

---

FMINMAX_VEC

ARM64 FMINMAX_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23	o1	1-bit value
22	sz	1-bit value
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:11	opcode	5-bit value
10	1	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: F

Variants

Variant	Mnemonic Example	Description
Default	F

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

FMLAL_ELEM

ARM64 FMLAL_ELEM instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	Fixed value: 0
28:24	01111	Fixed bit pattern
23:22	size	Fixed value: 11
21	L	1-bit value
20	M	1-bit value
19:16	Rm	4-bit value (second source register)
15:12	opcode	4-bit value
11	H	1-bit value
10	0	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: B, BL, BX

Variants

Variant	Mnemonic Example	Description
Default	B

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
M,Rm	regfplim
H,L,M,Rm	velemidx0

Required Features

---

FMLAL_VEC

ARM64 FMLAL_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23:22	size	Fixed value: 11
21	0	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15	1	Fixed bit pattern
14:11	opcode	Fixed value: 1111
10	1	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: B, BL, BX

Variants

Variant	Mnemonic Example	Description
Default	B

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

Required Features

---

FMLA_VEC

ARM64 FMLA_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	Fixed value: 0
28:24	01110	Fixed bit pattern
23	o1	1-bit value
22	sz	1-bit value
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:10	110011	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: FMLV

Variants

Variant	Mnemonic Example	Description
Default	FML

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

FMOV_FROMGP

ARM64 FMOV_FROMGP instruction

Encoding

Bits	Field	Description
31	sf	1-bit value (0=32-bit, 1=64-bit)
30	0	Fixed bit pattern
29	S	Fixed value: 0
28:24	11110	Fixed bit pattern
23:22	ftype	2-bit value
21	1	Fixed bit pattern
20:19	rmode	2-bit value
18:16	opcode	Fixed value: 111
15:10	000000	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: MOV, MOVS, MVN

Variants

Variant	Mnemonic Example	Description
Default	MOV

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	General-purpose register

Required Features

---

FMOV_IMM

ARM64 FMOV_IMM instruction

Encoding

Bits	Field	Description
31:24	00011110	Fixed bit pattern
23:22	ftype	2-bit value
21	1	Fixed bit pattern
20:13	imm8	8-bit value
12:5	10000000	Fixed bit pattern
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: MOV, MOVS, MVN

Variants

Variant	Mnemonic Example	Description
Default	MOV

Default Operands:

Parameter	Type
Rd	Floating-point register
imm8	immfmov

Required Features

---

FMOV_TOGP

ARM64 FMOV_TOGP instruction

Encoding

Bits	Field	Description
31	sf	1-bit value (0=32-bit, 1=64-bit)
30	0	Fixed bit pattern
29	S	Fixed value: 0
28:24	11110	Fixed bit pattern
23:22	ftype	2-bit value
21	1	Fixed bit pattern
20:19	rmode	2-bit value
18:16	opcode	Fixed value: 110
15:10	000000	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: MOV, MOVS, MVN

Variants

Variant	Mnemonic Example	Description
Default	MOV

Default Operands:

Parameter	Type
Rd	General-purpose register
Rn	Floating-point register

Required Features

---

FMULX_SCALAR

ARM64 FMULX_SCALAR instruction

Encoding

Bits	Field	Description
31:30	01	Fixed bit pattern
29	U	Fixed value: 0
28:23	111100	Fixed bit pattern
22	sz	1-bit value
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:10	110111	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: MUL, MULS

Variants

Variant	Mnemonic Example	Description
Default	MUL

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

FMUL_ELEM

ARM64 FMUL_ELEM instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:23	011111	Fixed bit pattern
22	sz	1-bit value
21	L	1-bit value
20	M	1-bit value
19:16	Rm	4-bit value (second source register)
15:12	opcode	4-bit value
11	H	1-bit value
10	0	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)
-1	1	Fixed bit pattern
-2	1	Fixed bit pattern
-3	1	Fixed bit pattern
-4	0	Fixed bit pattern

Mnemonic

Examples: MUL, MULS

Variants

Variant	Mnemonic Example	Description
Default	MUL

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
M,Rm	regfplim
H,L,M	velemidx

---

FMULELEMFP16

ARM64 FMULELEMFP16 instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:22	0111100	Fixed bit pattern
21	L	1-bit value
20	M	1-bit value
19:16	Rm	4-bit value (second source register)
15:12	opcode	4-bit value
11	H	1-bit value
10	0	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: MUL, MULS

Variants

Variant	Mnemonic Example	Description
Default	MUL

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
M,Rm	regfplim
H,L,M	velemidx

Required Features

FP16

---

FMULELEMSCALAR

ARM64 FMULELEMSCALAR instruction

Encoding

Bits	Field	Description
31:30	01	Fixed bit pattern
29	U	1-bit value (0=signed, 1=unsigned)
28:23	111111	Fixed bit pattern
22	sz	1-bit value
21	L	1-bit value
20	M	1-bit value
19:16	Rm	4-bit value (second source register)
15:12	opcode	4-bit value
11	H	1-bit value
10	0	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)
-1	1	Fixed bit pattern
-2	1	Fixed bit pattern

Mnemonic

Examples: MUL, MULS

Variants

Variant	Mnemonic Example	Description
Default	MUL

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
M,Rm	regfplim
H,L,M	velemidx

---

FMULELEMSCALAR_FP16

ARM64 FMULELEMSCALAR_FP16 instruction

Encoding

Bits	Field	Description
31:30	01	Fixed bit pattern
29	U	1-bit value (0=signed, 1=unsigned)
28:22	1111100	Fixed bit pattern
21	L	1-bit value
20	M	1-bit value
19:16	Rm	4-bit value (second source register)
15:12	opcode	4-bit value
11	H	1-bit value
10	0	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: MUL, MULS

Variants

Variant	Mnemonic Example	Description
Default	MUL

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
M,Rm	regfplim
H,L,M	velemidx

Required Features

FP16

---

FMUL_VEC

ARM64 FMUL_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:23	011100	Fixed bit pattern
22	sz	1-bit value
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:10	110111	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: MUL, MULS

Variants

Variant	Mnemonic Example	Description
Default	MUL

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

FP162REGSCALAR

ARM64 FP162REGSCALAR instruction

Encoding

Bits	Field	Description
31:30	01	Fixed bit pattern
29	U	1-bit value (0=signed, 1=unsigned)
28:24	11110	Fixed bit pattern
23	a	1-bit value
22:17	111100	Fixed bit pattern
16:12	opcode	5-bit value
11:10	10	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: Instruction

Variants

Variant	Mnemonic Example	Description
Default	h

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

Required Features

FP16

---

FP162REGVEC

ARM64 FP162REGVEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23	a	1-bit value
22:17	111100	Fixed bit pattern
16:12	opcode	5-bit value
11:10	10	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: B, BL, BX

Variants

Variant	Mnemonic Example	Description
Default	B

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

Required Features

FP16

---

FP163REGSCALAR

ARM64 FP163REGSCALAR instruction

Encoding

Bits	Field	Description
31:30	01	Fixed bit pattern
29	U	1-bit value (0=signed, 1=unsigned)
28:24	11110	Fixed bit pattern
23	a	1-bit value
22:21	10	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:14	00	Fixed bit pattern
13:11	opcode	3-bit value
10	1	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: SABD, UABD, SABA, UABA

Variants

Variant	Mnemonic Example	Description
Default	SABD

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

Required Features

FP16

---

FP163REGVEC

ARM64 FP163REGVEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23	a	1-bit value
22:21	10	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:14	00	Fixed bit pattern
13:11	opcode	3-bit value
10	1	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: ADD, ADDS

Variants

Variant	Mnemonic Example	Description
Default	ADD

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

Required Features

---

FPHORZSCALAR

ARM64 FPHORZSCALAR instruction

Encoding

Bits	Field	Description
31:30	01	Fixed bit pattern
29	U	1-bit value (0=signed, 1=unsigned)
28:24	11110	Fixed bit pattern
23:22	size	2-bit value (element size)
21:17	11000	Fixed bit pattern
16:12	opcode	Fixed value: 011xx
11:10	10	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: ADD, ADDS

Variants

Variant	Mnemonic Example	Description
Default	ADD

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

Required Features

---

FPHORZVEC

ARM64 FPHORZVEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23:22	size	Fixed value: x0
21:17	11000	Fixed bit pattern
16:12	opcode	Fixed value: 011xx
11:10	10	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: FV

Variants

Variant	Mnemonic Example	Description
Default	FV

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

Required Features

---

FRECP_SCALAR

ARM64 FRECP_SCALAR instruction

Encoding

Bits	Field	Description
31:30	01	Fixed bit pattern
29	U	1-bit value (0=signed, 1=unsigned)
28:23	111101	Fixed bit pattern
22	sz	1-bit value
21:14	10000111	Fixed bit pattern
13	o1	1-bit value
12:10	110	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: F

Variants

Variant	Mnemonic Example	Description
Default	F

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

---

FRECPSTEPSCALAR

ARM64 FRECPSTEPSCALAR instruction

Encoding

Bits	Field	Description
31:30	01	Fixed bit pattern
29	U	Fixed value: 0
28:24	11110	Fixed bit pattern
23	o1	1-bit value
22	sz	1-bit value
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:10	111111	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: FS

Variants

Variant	Mnemonic Example	Description
Default	FS

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

FRECPSTEPVEC

ARM64 FRECPSTEPVEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	Fixed value: 0
28:24	01110	Fixed bit pattern
23	o1	1-bit value
22	sz	1-bit value
21	1	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:10	111111	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: FSV

Variants

Variant	Mnemonic Example	Description
Default	FS

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register

---

FRECP_VEC

ARM64 FRECP_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23:22	size	2-bit value (element size)
21:13	100001110	Fixed bit pattern
12	o1	1-bit value
11:10	10	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: E

Variants

Variant	Mnemonic Example	Description
Default	E

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

---

FRINT

ARM64 FRINT instruction

Encoding

Bits	Field	Description
31	M	Fixed value: 0
30	0	Fixed bit pattern
29	S	Fixed value: 0
28:24	11110	Fixed bit pattern
23:22	ftype	2-bit value
21:18	1001	Fixed bit pattern
17:15	rmode	3-bit value
14:10	10000	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: FRINT

Variants

Variant	Mnemonic Example	Description
Default	FRINT

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

Required Features

---

FRINTTS

ARM64 FRINTTS instruction

Encoding

Bits	Field	Description
31	M	Fixed value: 0
30	0	Fixed bit pattern
29	S	Fixed value: 0
28:24	11110	Fixed bit pattern
23:22	ftype	2-bit value
21:17	10100	Fixed bit pattern
16:15	op	2-bit value
14:10	10000	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: FRINT

Variants

Variant	Mnemonic Example	Description
Default	FRINT

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

Required Features

FRINTTS

---

FRINTTS_VEC

ARM64 FRINTTS_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:23	011100	Fixed bit pattern
22	sz	1-bit value
21:13	100001111	Fixed bit pattern
12	o1	1-bit value
11:10	10	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: FRINT

Variants

Variant	Mnemonic Example	Description
Default	FRINT

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

Required Features

FRINTTS

---

FRINT_VEC

ARM64 FRINT_VEC instruction

Encoding

Bits	Field	Description
31	0	Fixed bit pattern
30	Q	1-bit value (0=smaller variant, 1=larger variant)
29	U	1-bit value (0=signed, 1=unsigned)
28:24	01110	Fixed bit pattern
23	o2	1-bit value
22	sz	1-bit value
21:13	100001100	Fixed bit pattern
12	o1	1-bit value
11:10	10	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: FRINT

Variants

Variant	Mnemonic Example	Description
Default	FRINT

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

---

System

Instruction	Description
MSR_FLAGM	System instruction
MSR_IMM	System instruction
MSR_REG	System instruction
SYS	System instruction

MSR_FLAGM

ARM64 MSR_FLAGM instruction

Encoding

Bits	Field	Description
31:19	1101010100000	Fixed bit pattern
18:16	op1	Fixed value: 000
15:12	0100	Fixed bit pattern
11:8	CRm	4-bit value
7:5	op2	3-bit value
4:0	11111	Fixed bit pattern

Mnemonic

Examples: Instruction

Variants

Variant	Mnemonic Example	Description
Default	Instruction

Default Operands:

Parameter	Type
CRm	Constant value

Required Features

---

MSR_IMM

ARM64 MSR_IMM instruction

Encoding

Bits	Field	Description
31:19	1101010100000	Fixed bit pattern
18:16	op1	3-bit value
15:12	0100	Fixed bit pattern
11:8	CRm	4-bit value
7:5	op2	3-bit value
4:0	11111	Fixed bit pattern

Mnemonic

Examples: B, BL, BX

Variants

Variant	Mnemonic Example	Description
Default	MSRi
1	MSRi
Sm	STR

Default Operands:

Parameter	Type
op1	Immediate value
op2	Immediate value
CRm	Immediate value

1 Operands:

Parameter	Type
CRm	Immediate value

Required Features

---

MSR_REG

ARM64 MSR_REG instruction

Encoding

Bits	Field	Description
31:22	1101010100	Fixed bit pattern
21	SYSL	1-bit value
20:5	sysreg	Fixed value: 1xxxxxxxxxxxxxxx
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: M # TODO: pretty format of sysreg

Variants

Variant	Mnemonic Example	Description
Default	M

Default Operands:

Parameter	Type
{SYSL:0	:1=Rt=reggp}
sysreg	Unsigned immediate
{SYSL:0	Rt=reggp:1=}

---

SYS

ARM64 SYS instruction

Encoding

Bits	Field	Description
31:22	1101010100	Fixed bit pattern
21	SYSL	1-bit value
20:5	sysreg	Fixed value: 01xxxxxxxxxxxxxx
4:0	Rt	5-bit value (destination register)

Mnemonic

Examples: SYS # TODO: pretty format of sysreg

Variants

Variant	Mnemonic Example	Description
Default	SYS
At	AT
Brb	B
Specres	Instruction
Dc	DC
Ic	IC
Tlbi_rme	B
Tlbi_os	B
Tlbi_range	B
Tlbi_w	B
Tlbi_xs	B

Default Operands:

Parameter	Type
{SYSL:0	:1=Rt=reggp}
sysreg	Unsigned immediate
{SYSL:0	Rt=reggp:1=}

At Operands:

Parameter	Type
Rt	General-purpose register

Brb Operands:

Parameter	Type
Rt	Zero register

Specres Operands:

Parameter	Type
Rt	General-purpose register

Dc Operands:

Parameter	Type
Rt	General-purpose register

Ic Operands:

Parameter	Type
Rt

Tlbi_rme Operands:

Parameter	Type
Rt

Tlbi_os Operands:

Parameter	Type
Rt

Tlbi_range Operands:

Parameter	Type
Rt	General-purpose register

Tlbi_w Operands:

Parameter	Type
Rt	General-purpose register

Tlbi_xs Operands:

Parameter	Type
Rt	General-purpose register

---

Cryptography

Instruction	Description
AES	Cryptography instruction
XAR	Cryptography instruction

AES

ARM64 AES instruction

Encoding

Bits	Field	Description
31:24	01001110	Fixed bit pattern
23:22	size	Fixed value: 00
21:14	10100001	Fixed bit pattern
13:12	opc	2-bit value
11:10	10	Fixed bit pattern
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: AES

Variants

Variant	Mnemonic Example	Description
Default	AES

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register

Required Features

---

XAR

ARM64 XAR instruction

Encoding

Bits	Field	Description
31:21	11001110100	Fixed bit pattern
20:16	Rm	5-bit value (second source register)
15:10	imm6	6-bit value
9:5	Rn	5-bit value (first source register)
4:0	Rd	5-bit value (destination register)

Mnemonic

Examples: XAR

Variants

Variant	Mnemonic Example	Description
Default	XAR

Default Operands:

Parameter	Type
Rd	Floating-point register
Rn	Floating-point register
Rm	Floating-point register
imm6	Immediate value

Required Features

SHA3

---